Reconfigurable Turbo Decoder Architecture for Multi-Standard SDR
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional turbo decoders are optimized for specific wireless standards and data rates, making them inefficient for software-defined radio (SDR) applications that require support for multiple standards and high data rates, leading to complex transceiver designs and high power consumption.
Innovation Solution
A reconfigurable turbo decoder architecture using context-based operation reconfigurable instruction set processors (CRISP) that supports multiple standards and data rates by utilizing multiple processing units, input data memories, and extrinsic information memories, allowing for parallel processing and adaptive power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional turbo decoders are optimized for specific wireless standards, then decoding performance for that standard is improved, but the device complexity and power consumption increase when supporting multiple standards
Solution Approach 1:
The patent implements a universal turbo decoder architecture that can decode multiple wireless standards (WCDMA, CDMA2000, IEEE-802.16e) using a single integrated design. The decoder uses configurable processing units with adjustable parameters (number of processing units N, memory sizes, data rates) that can be programmed to match different standard requirements, eliminating the need for separate dedicated decoders for each standard.
Solution Approach 2:
The decoder employs dynamic configuration capabilities where the number of active processing units N can be adjusted based on the data rate requirements of different standards. The architecture allows runtime reconfiguration of processing resources, memory allocation, and operational parameters to adapt to varying standard requirements, enabling efficient multi-standard support without fixed dedicated hardware for each standard.
2Speed
If conventional turbo decoders are optimized for low data rate standards, then power consumption is reduced, but the decoder cannot efficiently handle high data rate standards
Solution Approach 1:
The decoder dynamically adjusts the number of active processing units N based on the data rate requirements. For high data rate standards like WiBro and HSDPA, more processing units are activated to maintain throughput, while for lower data rates, fewer units are active to reduce power consumption. This dynamic resource allocation allows the same hardware to efficiently handle varying data rate requirements.
Solution Approach 2:
The architecture enables partial activation of processing resources based on actual needs. Instead of always running all N processing units at full capacity, the system activates only the necessary number of units required for the current data rate, avoiding excessive power consumption while maintaining the capability to handle high data rates when needed.
3Adaptability or versatility
If multiple turbo decoders are implemented to support multiple wireless standards, then support for different standards is improved, but chip space utilization becomes inefficient
Solution Approach 1:
The patent implements a universal turbo decoder architecture that can decode multiple wireless standards (WCDMA, CDMA2000, IEEE-802.16e) using a single integrated design. The decoder uses configurable processing units with adjustable parameters (number of processing units N, memory sizes, data rates) that can be programmed to match different standard requirements, eliminating the need for separate dedicated decoders for each standard.
Solution Approach 2:
The architecture merges the functionality of multiple standard-specific decoders into a single unified decoder. By combining the processing units, memory structures, and control logic into one integrated system that can be configured for different standards, the design achieves multi-standard support while significantly reducing the total chip area compared to implementing separate decoders for each standard.
Data Source
AI summary
A reconfigurable turbo decoder comprising N processing units. Each of the N processing units receives soft input data samples and decodes the received soft input data samples. The N processing units operate independently such that a first processing unit may be selected to decode the received soft input data samples while a second processing unit may be disabled. The number of processing units selected to decode the soft input data samples is determined by a data rate of the received soft input data samples. The reconfigurable turbo decoder also comprises N input data memories that store the received soft input data samples and N extrinsic information memories that store extrinsic information generated by the N processing units. Each of the N processing units is capable of reading from and writing to each of the N input data memories and each of the N extrinsic information memories.