Reconfigurable Turbo Interleaver for Multi-Standard Decoding
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Solution Overview
Problem
Existing turbo decoders require separate hardware for each supported standard, leading to increased chip area, design time, and material costs, as well as the need for costly redesigns when new standards are introduced, due to their inability to support multiple interleaving schemes.
Innovation Solution
A reconfigurable turbo decoding system with a polynomial-based address generator that can switch between different interleaving schemes using reconfiguration data, allowing a single hardware block to support multiple standards by reconfiguring the interleaver during operational use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate hardware blocks are implemented for each interleaving scheme to support multiple standards, then each standard can be supported reliably, but the chip area increases and design complexity increases
Solution Approach 1:
The address generator is designed as a universal hardware block that can perform multiple interleving schemes (first interleaving scheme and second interleaving scheme) through reconfiguration. The same hardware resources (adders, buffers, polynomial evaluator) are reused across different standards by loading different reconfiguration data, eliminating the need for separate dedicated hardware for each standard while maintaining full functional support for multiple interleaving schemes
Solution Approach 2:
The address generator incorporates dynamic reconfiguration capability that allows it to switch between different interleaving schemes during operational use. The system can load different reconfiguration data (polynomial coefficients, parameters) to adapt to different standards requirements, making the hardware flexible and adaptable rather than static and dedicated to a single function
2Reliability
If separate hardware blocks are implemented for each interleaving scheme, then each standard is fully supported, but design time increases and material costs increase
Solution Approach 1:
A single universal address generator design supports multiple interleaving schemes through reconfiguration, eliminating the need to design separate hardware blocks for each standard. The same hardware architecture can be configured for different standards by loading appropriate reconfiguration data, significantly reducing design time and reusable across multiple projects
Solution Approach 2:
The system supports different interleving schemes by changing parameters (polynomial coefficients, reconfiguration data) rather than changing the hardware structure itself. This allows the same hardware design to be reused for different standards by simply loading different parameter sets, reducing both design time and material costs
3Measurement precision
If conventional address generators use multiplication operations for polynomial evaluation, then accuracy is maintained, but hardware complexity increases
Solution Approach 1:
The system replaces multiplication operations with modular addition operations for polynomial evaluation in the address generator. By using modular addition instead of multiplication, the hardware complexity is significantly reduced (simpler adder circuits vs. complex multiplier circuits) while maintaining the necessary computational accuracy for generating interleaving addresses
Solution Approach 2:
The polynomial evaluation is transformed by changing the mathematical operation from multiplication to modular addition. This parameter change in the computational approach allows the same polynomial evaluation function to be implemented with simpler hardware, reducing device complexity while preserving the essential functionality and precision needed for address generation
Data Source
AI summary
A data processing system, a turbo decoding system, an address generator and a method of reconfiguring a turbo decoding method is provided. The data processing system (101) comprises the turbo decoding system (100). The turbo decoding system (100) comprises electronic circuits. The electronic circuits comprises: a memory (108), the address generator (102), and a Soft Input Soft Output decoder (106). The address generator (102) is operative to produce a sequence of addresses according to an interleaving scheme. The address generator can support multiple interleaving schemes. The address generator (102) is operative to receive reconfiguration information. The address generator (102) is operative to reconfigure during operational use the interleaving scheme in dependency on the reconfiguration information.