Reconstituted Substrate Structure for 3D Die Alignment and Thermal Control
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Solution Overview
Problem
Current 3D integration techniques in semiconductor devices face challenges such as sub-optimal thermal management due to coefficient of thermal expansion (CTE) mismatch between molding compound and semiconductor components, leading to device misalignment and warpage, which affects the reliability and performance of integrated circuits.
Innovation Solution
A method for forming reconstituted substrates by positioning semiconductor dies in cavities within substrates, filling voids with flowable materials, and forming conductive layers through vias, which are integrated with additional substrates to create a reconstituted substrate structure that enhances thermal management and reduces misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional packaging manufacturing processes use molding compound materials, then device packaging is achieved, but coefficient of thermal expansion mismatch occurs between molding compound and semiconductor components, causing device misalignment and warpage
Solution Approach 1:
The patent introduces a reconstituted substrate as an intermediary component between the molding compound and semiconductor components. This substrate has a coefficient of thermal expansion that matches the semiconductor components, serving as a thermal expansion mediator that prevents misalignment and warpage while still allowing conventional molding compound packaging processes to proceed
Solution Approach 2:
The patent changes the thermal expansion parameter by replacing the conventional molding compound directly contacting semiconductor components with a reconstituted substrate having matched CTE properties. This parameter change eliminates the thermal expansion mismatch problem while maintaining the packaging structure
2Quantity of substance
If wafer-to-wafer bonding techniques are used for heterogeneously stacking functional circuit partitions, then higher density is achieved, but the process complexity and difficulty increase
Solution Approach 1:
The patent performs preliminary actions by pre-attaching semiconductor components to individual substrate sections before final assembly. This allows components to be prepared and positioned in advance, simplifying the final stacking process while achieving high-density heterogeneous integration
3Productivity
If die-to-interposer stacking or die-to-wafer stacking approaches are used for SIC devices, then 3D integration is achieved, but thermal management remains sub-optimal
Solution Approach 1:
The reconstituted substrate serves as a thermal intermediary with improved thermal conductivity properties compared to conventional molding compounds. It maintains the 3D integration structure while providing superior heat dissipation pathways from semiconductor components
Solution Approach 2:
The patent employs composite material construction for the reconstituted substrate, combining materials with optimized thermal conductivity and matched coefficient of thermal expansion. This composite structure achieves both high integration density and improved thermal management
Data Source
AI summary
The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.