Reconstituted Wafer Bridge Die Alignment for Multi-Chip Modules
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Solution Overview
Problem
Conventional methods for forming multi-chip modules are costly and difficult, requiring complex processes and high precision to align and interconnect integrated circuit dies effectively.
Innovation Solution
The method involves forming a reconstituted wafer by molding integrated circuit dies with a molding layer, creating conductive routing through redistribution layers and conductive posts to align and interconnect multiple dies, reducing the complexity and cost by using a bridge die to align and connect upper IC dies, and optionally incorporating through-mold vias and a mezzanine redistribution layer for enhanced interconnectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form multi-chip modules with precise alignment and interconnection, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies preliminary action by forming a reconstituted wafer that pre-integrates multiple IC dies with their interconnect structures (through-mold vias, redistribution layers) before final module assembly. This pre-assembly approach performs alignment and interconnection work in advance, reducing the complexity of subsequent packaging operations while maintaining precise alignment through the molded structure's inherent geometric relationships.
Solution Approach 2:
The patent uses an intermediary reconstituted wafer structure that mediates between individual IC dies and the final multi-chip module. This intermediate structure includes molded encapsulant material and integrated interconnect elements that facilitate alignment and electrical connection, simplifying the overall manufacturing process by providing a standardized interface for module assembly.
2Reliability
If conventional multi-chip module formation processes are used, then interconnection reliability is improved, but manufacturing cost and difficulty increase
Solution Approach 1:
The patent merges multiple manufacturing operations into a single reconstituted wafer formation process. Through-mold vias, redistribution layers, and die attachment are combined into one integrated molding operation, reducing the number of discrete steps required. This consolidation maintains interconnection reliability by ensuring all elements are formed under controlled conditions while significantly improving manufacturing ease through process integration.
Solution Approach 2:
The patent applies parameter changes by transitioning from traditional discrete assembly parameters to a molded reconstitution process with different controlling parameters (mold cavity geometry, encapsulant material properties, curing conditions). This parameter transformation enables a shift from precision mechanical assembly to a more forgiving molded structure formation, improving ease of manufacture while maintaining reliability through the robustness of the molded interconnect structure.
3Reliability
If through-substrate vias are used for interconnection, then electrical connectivity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent uses copying by creating through-mold vias that replicate the electrical interconnection function without requiring actual substrate penetration. The molded vias copy the connectivity pattern needed for electrical interconnection, providing sufficient electrical pathways through the encapsulant material to achieve the required connectivity while avoiding the complexity of forming true through-substrate vias in the IC dies themselves.
Data Source
AI summary
Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.