Reconstituted Wafer BVA Layout for Fine-Pitch Testing Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current microelectronic packaging technologies face challenges in efficiently forming and testing microelectronic units with high-density interconnects, particularly in achieving compact sizes and facilitating high-speed operations while ensuring reliable mechanical and electrical connections across stacked arrangements.
Innovation Solution
The development of a microelectronic package with a redistribution structure and electrically conductive connector elements, where the connector elements have ends adjacent to the package sides, allowing for electrical coupling between external components, and a method for forming these packages involves creating a carrier with attachment regions, forming connector elements, and encapsulating them with a dielectric layer to enable efficient singulation into individual units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If chip scale packages are used to reduce assembly size, then the area occupied on circuit board is minimized, but the complexity of forming and testing high-density interconnects increases
Solution Approach 1:
The patent segments the interconnect formation process into multiple stages: first forming bond vias through the substrate, then forming conductor traces on the first surface, and finally forming additional bond vias through the traces. This segmentation allows each stage to be optimized independently, reducing the overall complexity of creating high-density interconnects in compact chip scale packages.
Solution Approach 2:
The patent utilizes the vertical dimension by forming bond vias that extend through the substrate thickness, allowing interconnects to be established in three dimensions rather than just on the surface. This enables high-density interconnection while maintaining a compact footprint on the circuit board, as connections are made both laterally and vertically.
2Productivity
If stacked arrangements of packages are used to increase integration density, then multiple chips can be mounted within a single footprint, but the difficulty of ensuring reliable mechanical and electrical connections across stacks increases
Solution Approach 1:
The patent performs preliminary actions by forming the bond vias and conductor traces on the substrate before mounting the semiconductor device. This ensures that the interconnect structure is already in place and can reliably support the device, facilitating dependable electrical connections in stacked arrangements without requiring additional connection steps after stacking.
Solution Approach 2:
The substrate acts as an intermediary element between stacked semiconductor devices, providing a stable mechanical and electrical interface. The bond vias and conductor traces formed on the substrate create reliable connection points that facilitate both mechanical support and electrical interconnection across multiple stacked packages.
3Speed
If fine pitch bond via arrays are used to achieve high-speed operations, then signal propagation time is reduced, but the manufacturing precision required for forming and testing increases
Solution Approach 1:
The bond vias are formed preliminarily through the substrate before the semiconductor device is mounted. This preliminary formation allows for precise control of via location and dimensions using standard semiconductor fabrication techniques, achieving the required fine pitch accuracy without needing ultra-precise alignment during device mounting and testing.
Solution Approach 2:
The patent replaces mechanical drilling or punching methods for creating bond vias with a chemical etching process. This substitution allows for more precise control of via dimensions and positioning, enabling fine pitch arrays to be formed with higher manufacturing precision compared to mechanical methods.
Data Source
AI summary
A microelectronic assembly having a first side and a second side opposite therefrom is disclosed. The microelectronic assembly may include a microelectronic element having a first face, a second face opposite the first face, a plurality of sidewalls each extending between the first and second faces, and a plurality of element contacts. The microelectronic assembly may also include an encapsulation adjacent the sidewalls of the microelectronic element. The microelectronic assembly may include electrically conductive connector elements each having a first end, a second end remote from the first end, and an edge surface extending between the first and second ends, wherein one of the first end or the second end of each connector element is adjacent the first side of the package. The microelectronic assembly may include a redistribution structure having terminals, the redistribution structure adjacent the second side of the package, the terminals being electrically coupled with the connector elements.