Reconstituted Wafer Multi-Chip Module Assembly for Precise Die Alignment
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Solution Overview
Problem
Conventional methods for forming multi-chip modules are costly and difficult, necessitating a more efficient and cost-effective approach.
Innovation Solution
A method involving wafer-level processing of a reconstituted wafer, where integrated circuit dies are molded with a molding layer and interconnected using conductive posts and redistribution layers to form multi-chip modules, allowing for alignment and electrical connectivity between dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to form multi-chip modules, then the modules can be manufactured with existing processes, but the manufacturing cost is high and the process complexity is difficult
Solution Approach 1:
The patent merges multiple separate manufacturing steps into a unified wafer-level process. Multiple dies are processed simultaneously on a single wafer substrate, combining die attachment, conductor formation, and interconnection steps that would traditionally be performed separately on individual chips, thereby reducing overall process complexity and manufacturing cost
Solution Approach 2:
The patent transitions from conventional chip-by-chip processing to wafer-level processing, adding a dimensional aspect to the manufacturing approach. By processing multiple dies simultaneously on a wafer substrate rather than handling individual chips sequentially, the method reduces process steps and improves manufacturing efficiency
2Productivity
If wafer-level processing is used to reduce cost and complexity, then manufacturing efficiency improves, but precise alignment and electrical connectivity between dies must be achieved
Solution Approach 1:
The patent performs preliminary alignment and conductor formation actions at the wafer level before die separation. Conductors are formed extending from die surfaces while dies are still positioned on the wafer substrate, establishing electrical connectivity pathways in advance. This preliminary action ensures precise alignment and connectivity is achieved before the complex die separation and attachment process
Solution Approach 2:
The patent introduces a wafer substrate as an intermediary element that holds multiple dies in precise relative positions during processing. The substrate acts as a temporary carrier that maintains die alignment and facilitates conductor formation, then is removed after the dies are transferred to their final package substrates, ensuring manufacturing precision without compromising productivity
Data Source
AI summary
Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.