3D Microelectronic Components via Reconstituted Wafer Metallization
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Solution Overview
Problem
Conventional microelectronics fabrication methods are limited in creating three-dimensional structures and through-substrate vias (TSVs) with feature thicknesses greater than 400 μm, which is insufficient for certain applications requiring thicker TSVs up to 1,000 μm or more.
Innovation Solution
A method involving the selection of a substrate, patterning of conductive materials on both surfaces, dicing into dies, securing and encapsulating these dies to form a reconstituted wafer, and further metallization to create thick, vertically oriented metal features, allowing for the formation of inductors and TSVs with enhanced thickness and aspect ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional microelectronics fabrication techniques are used to deposit and pattern layers of conductive material, then thin conductive layers can be formed, but the feature thickness is limited to less than 400 μm and cannot achieve the required 1,000 μm or more
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: initial patterning of conductive material, dicing into dies, encapsulation to form reconstituted wafer, and additional metallization. This segmentation allows the total thickness to accumulate across multiple processing steps rather than attempting to deposit a single thick layer, thereby achieving 1,000 μm or more while maintaining manufacturing precision at each individual step.
Solution Approach 2:
Conductive material is patterned on the substrate before dicing and encapsulation, establishing the initial conductive features. Subsequent metallization steps add additional thickness. This preliminary action allows precise control of the base layer while enabling later thickness enhancement without compromising the precision of the initial pattern formation.
2Adaptability or versatility
If additional transistors or features are added to increase device functionality, then the device surface area must be increased, but this reduces the number of devices that can be formed on a single wafer
Solution Approach 1:
The patent transitions from two-dimensional planar device architecture to three-dimensional vertical structures through the formation of thick conductive features extending through the substrate. This dimensional change allows additional functionality to be integrated vertically rather than requiring increased surface area, thereby maintaining high device density while enhancing functionality.
Solution Approach 2:
Multiple functional elements are integrated within the vertical structure of the reconstituted wafer, with conductive features, dies, and interconnects nested in three-dimensional space. This nesting approach allows multiple functions to coexist within the same footprint, increasing adaptability without reducing productivity.
3Length of stationary object
If through-substrate vias with thickness greater than 400 μm are formed using conventional methods, then the manufacturing process becomes infeasible, but applications require TSVs up to 1,000 μm or more
Solution Approach 1:
The via formation process is segmented into multiple manageable steps: initial conductive material deposition, dicing into dies, encapsulation in reconstituted wafer, and sequential metallization. Each step operates within conventional manufacturing capabilities, avoiding the need to form a single 1,000 μm thick layer in one operation, thereby maintaining ease of manufacture while achieving the required via thickness.
Solution Approach 2:
The substrate is diced and encapsulated into a reconstituted wafer before final metallization, creating a stable structure that can withstand subsequent thick metal deposition. This preliminary structuring makes the subsequent thick via formation feasible by providing mechanical support and defining the final geometry, rather than attempting to form thick vias in a single unsupported deposition step.
Data Source
AI summary
Aspects and examples include electrical components and methods of forming electrical components. In one example, a method includes selecting a substrate, forming a pattern of a first conductive material on a top surface of the substrate, forming a pattern of a second conductive material on a bottom surface of the substrate, dicing the substrate into one or more die having a first diced surface and a second diced surface, securing the first diced surface of each of the one or more die to a retaining material, encapsulating the one or more die in an encapsulent to form a reconstituted wafer, and forming a pattern of a third conductive material on the second diced surface by metalizing a surface of the reconstituted wafer.