Reconstructing Verification Test Graphs from Truncated Logs

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Solution Overview

Problem

Current post-silicon verification debugging methods face challenges in reconstructing a graph representation of a verification test due to limitations in circular buffer resources, which often result in truncated log data, missing start and end messages, and making it difficult to determine the actual order of actions during execution.

Innovation Solution

A method and system that utilize a processor to obtain and analyze truncated chronicle messages of start and end times of actions, reconstructing the graph representation based on a validated scenario, and automatically implanting print commands to determine the order of actions, allowing for the reconstruction of the graph representation of a previously executed verification test.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If all execution events are recorded during verification test execution, then complete debugging information is obtained, but circular buffer resources are quickly exhausted resulting in truncated log data

Engineering Contradiction:
Improvedebugging information completenessVSAvoidcircular buffer capacity
Core Design Contradiction:
Loss of informationVSQuantity of substance

Solution Approach 1:

The patent extracts only the essential debugging information (start and end messages of actions) from the complete execution events, storing only these critical markers in the circular buffer. This extraction approach maintains the ability to reconstruct execution flow while significantly reducing the data volume required, thus preventing buffer exhaustion while preserving debugging capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of recording all execution events completely, the patent implements partial recording by capturing only the necessary start and end markers of actions. This partial action approach provides sufficient information for debugging and execution path reconstruction without the excessive data storage requirements of complete event logging.

Inventive Principle:
Principle #16Partial or excessive action

2Quantity of substance

If truncated log data is used due to buffer limitations, then circular buffer resources are preserved, but the ability to determine actual order of actions is degraded

Engineering Contradiction:
Improvecircular buffer utilizationVSAvoidexecution order determination accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The patent performs preliminary action by recording the start and end messages with their timestamps during execution. These pre-recorded markers serve as anchors that enable accurate reconstruction of the execution order even when intermediate events are truncated. The timestamps provide the necessary temporal information to determine the actual sequence of actions without requiring complete log data.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The start and end messages act as intermediary elements that mediate between the truncated log data and the execution order determination. These markers serve as reference points that allow the system to reconstruct the actual execution sequence despite missing intermediate events, effectively bridging the gap between incomplete data and accurate order determination.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If complete execution events are logged, then accurate execution path reconstruction is possible, but debugging tool complexity increases

Engineering Contradiction:
Improveexecution path reconstruction accuracyVSAvoiddebugging tool complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The debugging tool extracts only the essential start and end messages from execution events, storing merely these critical markers. This extraction simplifies the data structure and reduces the complexity of processing, parsing, and analyzing execution logs, while still providing sufficient information for accurate execution path reconstruction.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of storing complete execution events and then filtering them for analysis, the patent inverts the approach by recording only the necessary start and end markers from the beginning. This inversion simplifies the debugging tool's workload by eliminating the need to process and filter large volumes of complete event data, reducing overall system complexity.

Inventive Principle:
Principle #13The other way round (Inversion)

4Ease of operation

If start and end messages are automatically implanted in test code, then execution order determination is simplified, but test code modification is required

Engineering Contradiction:
Improveexecution order determination easeVSAvoidtest code implementation ease
Core Design Contradiction:
Ease of operationVSEase of manufacture

Solution Approach 1:

The system performs preliminary action by automatically implanting start and end messages in the test code before execution. This preliminary instrumentation of the code simplifies the debugging process by ensuring that the necessary markers are already in place, making execution order determination straightforward without requiring manual code analysis or post-processing of complete event logs.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10579761B1Method and system for reconstructing a graph presentation of a previously executed verification test
Publication Date: 2020.03.03 CADENCE DESIGN SYST INC
  • US10579761B1 patent drawing
  • US10579761B1 patent drawing
  • US10579761B1 patent drawing

AI summary

A method for reconstructing a graph representation of a previously executed verification test, may include obtaining a truncated chronicle of start time and end time messages of actions of the verification test that were logged during execution of the verification test on a design under test (DUT); using a processor, parsing and analyzing the start time and the end time messages to determine an order of the actions; using a processor, determining an order of other actions of said verification test, based on a graph representation of a verified scenario from which the verification test was generated; and reconstructing the graph representation of the verification test based on the determined order of the actions and order of the other actions.