Reconstructed 3DIC Stitching Dies for Dense Multi-Layer Interconnects
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Solution Overview
Problem
Conventional 3D stacked integrated circuit (3DIC) packaging approaches are limited by passive silicon interposers and coarse interconnect density, requiring larger bottom die sizes and yielding low interconnect density, while also being restricted to a specific footprint, which hinders efficient communication between dies.
Innovation Solution
The proposed solution involves reconstructing 3DIC structures where each die functions as both a functional chip and a stitching device, forming a communication bridge between adjacent dies, using hybrid bonding and microbumps to create a high-density interconnect fabric, allowing for reduced die sizes and flexible communication paths between all package levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If conventional 3DIC packaging approaches use passive silicon interposers and die-to-die stacking, then structural stability is improved, but interconnect density deteriorates and device footprint increases
Solution Approach 1:
The patent merges the structural support function and interconnection function into a single integrated silicon interposer. The interposer contains both functional dies and stitching dies that provide mechanical support and electrical interconnection simultaneously, eliminating the need for separate passive support structures while achieving high interconnect density through the stitching die network.
Solution Approach 2:
The stitching dies in the interposer serve multiple functions: they provide mechanical structural stability, establish electrical interconnections between adjacent dies, and enable signal routing. This multi-functionality allows the same structural element to simultaneously improve stability while increasing interconnect density, resolving the technical contradiction.
2Ease of manufacture
If conventional 3DIC approaches use a super-set footprint bottom die, then manufacturing simplicity is improved, but adaptability deteriorates
Solution Approach 1:
The interposer is segmented into multiple stitching dies arranged in a grid pattern, each capable of independently supporting and interconnecting adjacent functional dies. This segmentation allows the interposer to be manufactured using standard wafer fabrication processes while providing flexible adaptation to different die layouts and package footprints, as the stitching die network can be configured to match various design requirements.
3Device complexity
If conventional packaging uses coarse interconnect density, then manufacturing complexity is reduced, but communication latency increases
Solution Approach 1:
The patent changes the interconnect density parameter from coarse to fine by implementing a high-density stitching die network in the interposer. The stitching dies are arranged in a dense grid pattern with small pitch, enabling short communication paths between adjacent functional dies. This parameter change reduces communication latency while maintaining manufacturing feasibility through standardized semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a full 3DIC interconnect fabric among all dies, providing high connection density, lower latency, and smaller z-height, while allowing for minimalist die functionality and flexible communication paths, overcoming the limitations of conventional packaging methods.
Implementation Method 1
bonding may be wafer-on-wafer in which the second plurality of dies is in a second reconstructed wafer, or chip-on-wafer where the second plurality of dies are discrete, and a second gap fill material is subsequently applied around the second plurality of dies after hybrid bonding
Data Source
AI summary
Reconstructed 3DIC structures and methods of manufacture are described. In an embodiment, one or more dies in each package level of a 3DIC are both functional chips and/or stitching devices for two or more dies in an adjacent package level. Thus, each die can function as a communication bridge between two other dies/chiplets in addition to performing a separate chip core function.