Reconstructed Wafer Edge Processing for Size Reduction and QC

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Solution Overview

Problem

Existing wafer-form packages face challenges in efficiently reducing the size of reconstructed wafers while maintaining quality control, as conventional sawing processes can expose dielectric layers and create quality check issues.

Innovation Solution

A combination of trimming and sawing processes is employed to form round and straight edges on reconstructed wafers, using a trimming blade for round edges and a sawing blade for straight edges, ensuring distinct trace directions to avoid exposing dielectric layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If conventional sawing processes are used to reduce wafer size, then wafer dimensions are reduced, but dielectric layers are exposed causing quality check issues

Engineering Contradiction:

Improvewafer sizeVSAvoidquality control

Core Design Contradiction:

Length of stationary objectVSManufacturing precision

Solution Approach 1:

The patent divides the edge formation process into two distinct segments: trimming (for round edges) and sawing (for straight edges). Each process targets specific portions of the wafer edge, allowing optimization of each process for its specific function while avoiding the defects that arise from using a single process for both purposes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different edge portions of the wafer are treated with different processes based on their specific requirements. Round edges are trimmed while straight edges are sawed, creating local quality differentiation that prevents dielectric layer exposure while maintaining the benefits of both edge types

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If trimming process is used to form round edges, then edge quality is improved, but wafer size reduction is less efficient compared to sawing

Engineering Contradiction:

Improveedge qualityVSAvoidwafer size reduction efficiency

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent segments the edge formation task between trimming and sawing processes. Trimming is applied to portions requiring round edges for quality, while sawing is applied to portions where straight edges suffice for size reduction, thus combining the quality benefits of trimming with the efficiency of sawing

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges two previously separate processes (trimming and sawing) into a combined workflow for edge formation. This integration allows the system to leverage the quality advantages of trimming and the efficiency advantages of sawing in a unified process sequence

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250329703A1Trimming and sawing processes in the formation of wafer-form packages

Publication Date: 2025.10.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes forming a reconstructed wafer, which includes placing a plurality of device dies over a carrier, encapsulating the plurality of device dies in an encapsulant, and forming a redistribution structure over the plurality of device dies and the encapsulant. The redistribution structure includes a plurality of dielectric layers and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes performing a trimming process on the reconstructed wafer. The trimming process forms a round edge for the reconstructed wafer. A sawing process is performed on the reconstructed wafer, so that the reconstructed wafer includes straight edges.