Heterogeneous Reconstructed Wafer Layout for Logic Die Stacking
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Solution Overview
Problem
Conventional semiconductor packaging processes face inefficiencies due to the need to accommodate larger dies on top of known good dies, leading to wasted wafer space and impractical sizing of smaller dies, which can result in failed semiconductor device assemblies.
Innovation Solution
The use of heterogenous reconstructed wafers, comprising known good logic dies and support dies, with gap-fill material and Through-Silicon Vias, allowing for efficient stacking and electrical isolation, while utilizing wafer space effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional packaging processes are used to accommodate larger dies on top of known good dies, then the stacking structure can be formed, but wafer space is wasted and smaller dies cannot be properly sized
Solution Approach 1:
The wafer is divided into multiple functional zones: known good dies (KGDs) in a first array, additional dies in a second array, and unused wafer space. This segmentation allows each die type to be optimally sized and positioned without forcing uniform sizing across all dies, thereby improving wafer space utilization while maintaining manufacturing practicality.
Solution Approach 2:
The patent transitions from a conventional single-array die arrangement to a multi-array three-dimensional stacked structure. By organizing dies in multiple arrays across different vertical levels (first array at lower level, second array at upper level), the system achieves better space utilization without compromising the manufacturability of individual die sizes.
2Quantity of substance
If smaller known good dies are used, then more dies can fit on the wafer, but larger additional dies cannot be properly supported
Solution Approach 1:
The wafer is segmented into different die arrays with different size characteristics. KGDs in the first array can be smaller to maximize quantity, while additional dies in the second array can be larger to ensure proper support and functionality. This segmentation resolves the contradiction by allowing size optimization for each die type's specific role in the stack.
Solution Approach 2:
Different regions of the wafer are assigned different die sizes based on local requirements. The first array region accommodates smaller KGDs for high density, while the second array region accommodates larger additional dies for structural support. This local quality approach ensures that each die size is appropriate for its specific function and position in the final assembly.
3Reliability
If larger dies are used to support additional dies, then stacking reliability improves, but wafer space utilization decreases
Solution Approach 1:
By transitioning to a multi-array three-dimensional arrangement, the patent allows larger support dies to be positioned in the second array at an upper level, while smaller KGDs occupy the first array at a lower level. This vertical dimensionality enables both large and small dies to coexist on the same wafer without competing for horizontal space, thus maintaining both support reliability and space utilization.
Data Source
AI summary
A method for manufacturing a heterogenous reconstructed wafer is provided. The method includes bonding a plurality of previously-tested main dies to a side of a silicon carrier wafer. The method also includes bonding a plurality of support dies to the side of the silicon carrier wafer such that the plurality of support dies is disposed in gaps between the plurality of main dies. The method also includes filling gaps between the plurality of main dies and the plurality of support dies with a gap-fill material such that the gap-fill material forms a gap-fill layer around and above each of the plurality of main dies and each of the plurality of support dies. The method then includes removing the silicon carrier wafer to form a heterogenous reconstructed wafer.