Recording Head Driver Using Dual-Edge Clock Timing Resolution
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Solution Overview
Problem
Existing serial transfer systems face challenges in increasing the resolution of signals to drive driven elements, such as recording heads, which requires high clock frequencies, leading to increased manufacturing costs and substrate area usage.
Innovation Solution
A driving device with a clock signal generating unit, input unit, timing generating units, logical circuit, and driving circuit that selectively uses rising or falling edges of a clock signal to generate pulse signals, allowing for higher resolution and reduced power consumption by doubling the effective period of the signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high clock frequency is used to increase signal resolution, then the time resolution is improved, but the manufacturing cost and substrate area increase
Solution Approach 1:
The patent utilizes both rising and falling edges of the clock signal periodically to generate timing signals. By alternating between positive-edge-triggered and negative-edge-triggered operations, the system achieves higher effective resolution without requiring a higher clock frequency, thus avoiding increased substrate area and manufacturing cost
Solution Approach 2:
The patent changes the operational parameter from single-edge triggering to double-edge triggering of the clock signal. This parameter change effectively doubles the timing resolution capability without increasing the clock frequency, thereby maintaining the same substrate area and manufacturing cost while achieving better signal resolution
2Measurement precision
If a high clock frequency is used to increase signal resolution, then the time resolution is improved, but the manufacturing cost increases
Solution Approach 1:
The patent employs periodic alternation between rising-edge and falling-edge triggering modes to achieve high-resolution timing signals. This approach allows the system to obtain fine time resolution using a moderate clock frequency, thereby reducing manufacturing cost while maintaining high signal resolution
Solution Approach 2:
By changing the triggering parameter from single-edge to double-edge detection, the system achieves higher effective resolution without increasing clock frequency. This parameter optimization reduces manufacturing complexity and cost while improving signal resolution
3Adaptability or versatility
If multiple systems with different clock frequencies are prepared to offset phases, then the signal phase control is improved, but the device complexity increases
Solution Approach 1:
The patent merges the functionality of multiple clock frequency systems into a single system by utilizing both rising and falling edges of one clock signal. This consolidation achieves the same phase control capability as multiple separate systems would provide, but with reduced device complexity and unified architecture
Solution Approach 2:
The clock signal serves multiple functions simultaneously by triggering both positive-edge and negative-edge operations. This multi-functional use of a single clock signal achieves versatile phase control without requiring separate systems for different frequencies, thereby reducing overall system complexity
Data Source
AI summary
According to an aspect of the present invention, a high-resolution, small-size, low-cost driving device includes a clock signal generating unit configured to receive a first clock signal of a differential signaling system and generate a second clock signal, an input unit configured to input a data signal which includes first information and second information, a first timing generating unit configured to select an edge of the second clock signal based on the first information and to generate a first signal by counting occurrences of the selected edge a second timing generating unit configured to select edge of the second clock signal based on the second information and to generate a second signal by counting occurrences of the selected edge, a logical circuit configured to generate a pulse signal based on the first and second signals, and a driving element configured to drive a driven element using the pulse signal.