Electronic Device Recording Pre-Malfunction System States
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Solution Overview
Problem
Existing electronic devices lack the capability to record system states before malfunctions occur, making it difficult to identify the root cause of system failures.
Innovation Solution
An electronic device is integrated with a request gate, response gate, monitor module, clock signal control module, and record module, which allow for the recording of request and response signals when a record instruction is received, enabling the capture of system states before malfunctions happen.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation software or simulation systems are used to imitate the operation of a real electronic device, then the possibility of system malfunction can be reduced, but the simulation is only capable of finding out the problems that the manufacturers assume and cannot predict all problems in the real electronic system
Solution Approach 1:
The patent implements preliminary action by equipping the electronic system with debugging members (debug bus, debug register, scan chain) before malfunction occurs. These components are pre-configured to capture and store system states, enabling post-event analysis of both pre-malfunction and post-malfunction states, thereby addressing the limitation of simulation software that can only predict assumed problems.
2Measurement precision
If a debug bus, debug register and scan chain are equipped in the electronic system for debugging, then the system state when malfunction occurs can be recorded, but the system state before malfunction cannot be recorded, making it unfavorable for finding the root cause
Solution Approach 1:
The patent applies preliminary action by implementing a hold signal mechanism that pauses the clock signal before malfunction occurs, thereby preserving the pre-malfunction system state in the debug members. This allows the system to record both the state leading up to malfunction and the state at malfunction, enabling comprehensive root cause analysis.
Solution Approach 2:
The patent introduces a hold signal as an intermediary mechanism between the clock signal and the system operation. This hold signal acts as a mediator that temporarily suspends the clock signal when abnormality is detected, allowing the system to maintain and record the pre-malfunction state without losing critical information.
3Loss of information
If the clock signal is stopped to record the system state, then the system state can be captured for analysis, but the system operation is interrupted
Solution Approach 1:
The patent extracts the clock signal control function from the main system operation by implementing independent control logic that selectively pauses the clock signal only when abnormality is detected. This extraction allows the system to maintain normal operation during typical functioning while capturing system states only when necessary, minimizing impact on productivity.
Solution Approach 2:
The patent implements feedback by continuously monitoring system operation and using the monitoring result to control the clock signal. When abnormality is detected, the feedback mechanism triggers the hold signal to pause the clock, enabling state recording. After recording is complete, the system resumes normal operation, thus balancing information capture with operational continuity.
Data Source
AI summary
An electronic device, for integration with functional circuit modules, includes gates, monitor module, signal control module and record module. The functional modules are operated on clock signal for generating request instruction and response signal. The gate is coupled to the functional modules for transmitting request instruction and response signal to functional module on enable signals. The monitor module is coupled to the functional modules and the gates for generating hold signal. The monitor module generates enable signals on finish signal. The clock signal control module coupled to the functional modules and the monitor module for outputs main clock signal to generate clock signals. The clock signal control module generates record instruction and stop clock signals, and the clock signal control module re-outputs clock signals on finish signal. The record module coupled to the functional modules and the clock signal control module begins to record request instruction and response signal when receiving record instruction.