Recoverable Ethernet Receiver Joint Decoder

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Solution Overview

Problem

Conventional communication receivers for gigabit Ethernet struggle to achieve the target 5.6 dB coding gain due to error propagation, especially in link segments longer than 100 meters, and fail to promptly detect and recover from errors caused by inter-symbol interference and channel crosstalk.

Innovation Solution

A recoverable Ethernet receiver is designed with a physical coding sublayer and a joint decision feedback equalizer and Trellis decoder that generates a check-idle value to differentiate between idle and data modes, using a seed value and polarity characterization to prevent error propagation, and includes a lookahead generator and decoding latency compensator to improve decoding accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate Viterbi decoder and ISI post-cursor equalizer are used, then device complexity is reduced, but coding gain cannot be satisfactorily achieved and error propagation occurs

Engineering Contradiction:
Improvecoding gainVSAvoiddecoder structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the Viterbi decoder and ISI post-cursor equalizer into a unified joint decoder structure. The soft-output Viterbi algorithm (SOVA) and decision feedback equalization are integrated within the same processing framework, allowing the decoder to simultaneously perform decoding and equalization functions. This merging eliminates the error propagation issue between separate components while achieving the target 5.6 dB coding gain through cooperative operation of the constituent elements.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If conventional transceiver architecture is used, then ease of manufacture is improved, but error propagation cannot be effectively prevented

Engineering Contradiction:
Improveerror propagation preventionVSAvoidtransceiver implementation
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent implements a feedback mechanism within the joint decoder where the output decisions from the soft-output Viterbi algorithm are fed back to the decision feedback equalizer component. This internal feedback loop allows the system to correct errors by using previously decoded information to refine current equalization decisions, effectively preventing error propagation while maintaining a manufacturable implementation through standardized feedback circuitry.

Inventive Principle:
Principle #23Feedback

3Length of stationary object

If link segment length exceeds 100 meters, then communication coverage is improved, but inter-symbol interference and channel crosstalk increase causing error catastrophe

Engineering Contradiction:
Improvelink segment lengthVSAvoidinter-symbol interference
Core Design Contradiction:
Length of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary equalization action through the decision feedback equalizer component that operates in conjunction with the Viterbi decoder. By预先 compensating for inter-symbol interference and channel crosstalk effects before the decoding process, the system prepares the received signal to be more resilient to degradation from extended link lengths. The feedback equalizer proactively cancels out anticipated interference patterns, enabling reliable communication beyond the standard 100-meter Ethernet limit.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8767883B2Recoverable Ethernet receiver
Publication Date: 2014.07.01 HIMAX TECH LTD
  • US8767883B2 patent drawing
  • US8767883B2 patent drawing
  • US8767883B2 patent drawing

AI summary

The present invention is directed to a recoverable Ethernet receiver. A joint decision feedback equalizer (DFE) and Trellis decoder is configured to decode a receiving signal to result in a received symbol, and configured to generate a check-idle value which is used to indicate an idle mode. A physical coding sublayer (PCS) block is configured to generate a seed value and a polarity characterization according to the received symbol, with the joint DFE and Trellis decoder generating the check-idle value according to the seed value and the polarity characterization.