Recovered Clock Filtering for Jitter-Stable Distributed Antenna Links
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Solution Overview
Problem
Distributed antenna systems face challenges in maintaining a stable master clock signal over unshielded twisted pair cables, leading to jitter and noise issues that affect RF frequency translation, especially in cost-sensitive applications where additional cabling is not feasible.
Innovation Solution
A method and system that generate a jitter-reduced clock signal using a phase-locked loop and loop filter to extract and stabilize the clock signal from a serial encoded binary data stream, allowing it to track long-term drift while filtering out short-term jitter, enabling effective clock recovery and scaling for distributed antenna systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If unshielded twisted pair cables are used for cost-effective deployment, then system cost is reduced, but jitter and crosstalk increase affecting clock stability
Solution Approach 1:
A loop filter is introduced as an intermediary component between the phase-locked loop and the clock output. This filter mediates the relationship between the unstable clock signal from the unshielded twisted pair cable and the required stable clock signal, selectively attenuating jitter and noise while preserving the essential clock signal and its drift characteristics.
Solution Approach 2:
A phase-locked loop with feedback mechanism is implemented to continuously monitor and correct clock signal deviations. The feedback loop compares the received clock signal with a reference, detects phase and frequency errors, and automatically adjusts to maintain synchronization, thereby compensating for the instability introduced by unshielded twisted pair cables.
2Reliability
If disciplined oscillators or fiber optics are used to maintain clock stability, then clock signal stability is improved, but system cost increases
Solution Approach 1:
The patent replaces expensive disciplined oscillators and fiber optic infrastructure with a cost-effective combination of unshielded twisted pair cables and signal processing circuitry. The system uses inexpensive components (loop filter, phase-locked loop) to achieve the required clock stability, eliminating the need for costly disciplined oscillators and fiber optic cables while maintaining functional equivalence.
3Measurement precision
If additional cables or wires are added for clock reference transmission, then clock synchronization accuracy is improved, but deployment complexity and cost increase
Solution Approach 1:
The existing serial data link cables are made multi-functional by embedding clock reference information within them. Instead of requiring separate dedicated clock cables, the system transmits both data and clock reference signals through the same unshielded twisted pair cables, eliminating additional infrastructure while maintaining synchronization accuracy.
Solution Approach 2:
The patent merges the clock reference transmission function with the existing data transmission function. By embedding the clock signal within the serial data link, the system combines multiple functions (data transmission and clock distribution) into a single cable infrastructure, reducing deployment complexity and eliminating the need for separate clock synchronization cables.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables cost-effective deployment of distributed antenna systems by maintaining clock stability over unshielded twisted pair cables, reducing jitter and noise, and supporting multiple communication standards, including cellular, public safety, and WiFi, without the need for additional cabling.
Implementation Method 1
generating a recovered clock signal that is phase locked to the encoded binary data stream with a phase-locked loop
Implementation Method 2
generating an error signal based on a difference between a phase of the encoded binary data stream and the recovered clock signal
Implementation Method 3
integrating the error signal with a loop filter configured with a bandwidth that allows the jitter and drift in the encoded binary data stream to generate a signal to control a voltage controlled oscillator
Implementation Method 4
generating a stable recovered clock signal by filtering the recovered clock signal to remove jitter without substantially affecting the frequency of the stable recovered clock signal
Implementation Method 5
generate a signal to control a voltage controlled oscillator
Implementation Method 6
producing at least one output clock by scaling the stable recovered clock signal frequency
Data Source
AI summary
Embodiments of the invention provide a method, distributed antenna system, and components that generate a jitter reduced clock signal from a binary encoded data stream transmitted over a communication medium. The method includes receiving a modulated signal that includes the binary encoded data stream and generating a recovered clock signal that is phase locked to the binary encoded data stream. The method further comprises generating a stable recovered clock signal by filtering the recovered clock signal to remove jitter, while allowing the clock signal to track long-term drift.