Recovery Pulses Counter Cumulative Read Disturb in SC-SGD Memory
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Solution Overview
Problem
Semi-circle drain-side select gate (SC-SGD) memory technology faces inefficiencies due to charge migration caused by neighboring electric fields, leading to program disturb during programming and erase operations, especially after repeated quick read operations.
Innovation Solution
A memory apparatus with a drain-side select gate transistor and a control means that determines a downshift recovery trigger event, inserting a predetermined idle time or a recovery pulse of negative voltage to the select gate transistor to mitigate charge migration and recover threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If etching technology is used to create semi-circular memory holes to reduce die size, then manufacturing efficiency and die size are improved, but the metal shielding layer is removed and charge migration occurs leading to program disturb
Solution Approach 1:
The patent applies preliminary anti-action by detecting the downshift of the drain-side select gate threshold voltage before program disturb occurs, and preemptively applying a recovery pulse or inserting idle time to counteract the charge migration effect. This prevents the program disturb issue from developing rather than reacting to it after occurrence.
Solution Approach 2:
The patent implements preliminary action by continuously monitoring the threshold voltage of the drain-side select gate and detecting downshift events early in the operation sequence. This early detection enables timely intervention through recovery pulses or idle time insertion before the charge migration causes program disturb during subsequent programming operations.
2Productivity
If repeated quick read operations are performed to improve productivity, then read speed and throughput are improved, but charge migration is cumulatively exacerbated leading to program disturb
Solution Approach 1:
The patent implements feedback by continuously monitoring the threshold voltage of the drain-side select gate and using this information to control subsequent operations. When a downshift is detected indicating cumulative charge migration from repeated reads, the system responds by inserting idle time or applying recovery pulses, thereby dynamically adjusting operation parameters based on real-time device state.
Solution Approach 2:
The patent applies periodic action by inserting predetermined idle time intervals or recovery pulses at regular intervals or upon detecting specific downshift thresholds during repeated read operations. This periodic intervention prevents cumulative charge migration from reaching levels that would cause program disturb, allowing sustained high-speed reading while maintaining reliability.
3Speed
If no recovery measures are taken to maintain operation speed, then memory operation speed is maintained, but threshold voltage downshift accumulates and program disturb occurs
Solution Approach 1:
The patent applies partial action by implementing recovery measures selectively rather than continuously. Recovery pulses or idle time are applied only when a downshift recovery trigger event is detected, not during every operation. This selective approach maintains high operation speed during normal conditions while preventing program disturb when charge migration becomes significant.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces program disturb and improves memory operation stability by addressing charge migration issues, enhancing the reliability of memory operations across various temperatures and read frequencies.
Implementation Method 1
a recovery pulse of a negative voltage to the drain-side select gate transistor of the plurality of memory holes of each of a plurality of strings of rows of the plurality of memory holes for a predetermined pulse period of time
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings and configured to retain a threshold voltage. The memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes. A control means determines whether a downshift recovery trigger event has occurred in memory operations. In response to determining the downshift recovery trigger event has occurred, the control means inserts at least one of a predetermined idle time in the memory operations and a recovery pulse of a negative voltage to the drain-side select gate transistor of the memory holes of the strings for a predetermined pulse period of time during one of the memory operations.