Rectangular Contact Lithography for ASIC Cost Reduction
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Solution Overview
Problem
Current optical lithography methods face challenges in reducing feature size below 100 nm due to limitations in resolution enhancement techniques, leading to increased manufacturing costs and complexity, particularly in the placement of contacts in standard cells of application-specific integrated circuits (ASICs), where regular placement in both directions is difficult and costly, and existing approaches require multiple exposures and extra masks.
Innovation Solution
A double-exposure photolithography method using a reusable chromeless alternating phase-shifting template mask and a trim mask to place rectangular contacts unrestrictedly in the height direction and regularly in the width direction, minimizing circuit area increase and reducing manufacturing costs by eliminating the need for extra application-specific masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-exposure lithography is used for contact placement, then manufacturing process is simple, but resolution below 100 nm cannot be achieved and feature size reduction is limited
Solution Approach 1:
The contact placement process is segmented into two separate exposures: first exposure places contacts regularly in the width direction using a reusable template mask, second exposure places contacts unrestrictedly in the height direction using an application-specific trim mask. This segmentation allows each exposure to be optimized for its specific purpose, achieving high precision while managing complexity.
Solution Approach 2:
The reusable template mask is prepared in advance with a periodic pattern that defines regular contact placement in the width direction. This preliminary action creates a foundation that can be reused across multiple applications, reducing the complexity of creating new masks for each design while maintaining high precision contact placement.
2Area of stationary object
If regular placement of contacts in both directions is implemented, then circuit area is reduced, but manufacturing cost increases due to multiple exposures and extra masks
Solution Approach 1:
The template mask is designed as a universal reusable component that can be applied across multiple different application-specific designs. By separating the regular width-direction placement (universal) from the unrestricted height-direction placement (application-specific), the system achieves regular placement benefits while reducing per-application manufacturing costs through mask reuse.
Solution Approach 2:
The contact placement is segmented into two functional components: regular placement in width direction (achieving area reduction) and unrestricted placement in height direction (maintaining design flexibility). This selective regular placement reduces circuit area without requiring full two-dimensional regular placement, thereby avoiding the need for multiple application-specific masks and reducing manufacturing costs.
3Area of moving object
If feature size is reduced below 100 nm, then transistor density increases, but existing lithography resolution enhancement techniques become insufficient and manufacturing complexity increases
Solution Approach 1:
The lithography process is segmented into two exposures with different purposes: the first exposure handles the challenging sub-100 nm regular placement in the width direction using a reusable template mask optimized for that resolution, while the second exposure handles the less demanding unrestricted placement in the height direction. This segmentation allows targeted optimization for sub-100 nm features without making the entire process overly complex.
Solution Approach 2:
The patent changes the parameters of the lithography process by using a chromeless alternating phase-shifting template mask with specific optical properties that enhance resolution for sub-100 nm features. The phase-shifting mechanism and material composition are specifically tuned to achieve the required resolution while managing the complexity of the lithography process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for more effective use of resolution enhancement technologies, reducing manufacturing costs and contact size, while maintaining design flexibility, although it may introduce additional layout complexity that requires a balance between design flexibility and manufacturability.
Implementation Method 1
a reusable chromeless alternating phase-shifting template mask and a trim mask. The rectangular contacts have a smaller dimension in the direction in which contacts are placed regularly.
Implementation Method 2
double-exposure photolithography method using a reusable template mask and a trim mask to image regularly-placed rectangular contacts
Data Source
AI summary
An optical lithography method is disclosed that uses double exposure of a reusable template mask and a trim mask to fabricate regularly-placed rectangular contacts in standard cells of application-specific integrated circuits (ASICs). A first exposure of the reusable template mask with periodic patterns forms periodic dark lines on a wafer and a second exposure of an application-specific trim mask remove the unwanted part of the dark lines and the small cuts of the dark lines left form the rectangular regularly-placed contacts. All contacts are placed regularly in one direction while unrestrictedly in the perpendicular direction. The regular placement of patterns on the template mask enable more effective use of resolution enhancement technologies, which in turn allows a decrease in manufacturing cost and the minimum contact size and pitch. Since there is no extra application-specific mask needed comparing with the conventional lithography method for unrestrictedly-placed contacts, the extra cost is kept to the lowest. The method of the invention can be used in the fabrication of standard cells in application-specific integrated circuits (ASICs) to improve circuit performance and decrease circuit area and manufacturing cost.