Rectangular Surround Gate Vertical FET for 3D Memory
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Solution Overview
Problem
Conventional vertical select field effect transistors in three-dimensional ReRAM devices suffer from suboptimum on-current and leakage current due to their dual channel configuration, where the pair of gate electrodes indirectly control electron flow along only two sidewalls of a rectangular pillar, leading to degradation of turn-on characteristics.
Innovation Solution
A two-dimensional array of surround gate field effect transistors is developed, featuring a ladder-shaped surround select gate electrode that surrounds the entire channel, improving on-current and control over electron flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a dual channel configuration with pair of gate electrodes is used to control electron flow, then the device structure is simpler, but the on-current and control over electron flow are suboptimum
Solution Approach 1:
The patent transitions from a conventional planar gate configuration to a vertical three-dimensional surround gate configuration. The gate electrode wraps around the channel in multiple dimensions, providing control over all four sidewalls of the rectangular channel cross-section. This dimensional change enables superior electrostatic control and higher on-current without proportionally increasing manufacturing complexity.
Solution Approach 2:
The gate electrode is configured to surround and enclose the channel, with the gate structure nested around the channel in a wraparound configuration. This nested arrangement allows the gate to control electron flow from multiple directions simultaneously, improving control effectiveness while maintaining a compact integrated structure.
2Ease of manufacture
If gate electrodes indirectly control electron flow along only two sidewalls, then the manufacturing process is easier, but the turn-on characteristics degrade
Solution Approach 1:
The invention moves from controlling only two sidewalls in a planar configuration to controlling all four sidewalls through a vertical surround gate structure. This dimensional transition enables complete perimeter control of the channel, significantly improving turn-on characteristics while using standard vertical fabrication techniques.
Solution Approach 2:
The gate electrode is divided into multiple segments or portions that collectively surround the channel. These segmented gate portions can be formed through sequential fabrication steps, with each segment contributing to the overall surround control. This segmentation approach makes the complex surround gate structure manufacturable using step-by-step standard processes.
3Reliability
If a ladder-shaped surround select gate electrode surrounds the entire channel, then on-current and control are improved, but the device structure becomes more complex
Solution Approach 1:
The patent employs a vertical three-dimensional surround gate configuration where the gate electrode wraps around the channel in the vertical dimension and extends along the channel length. This spatial arrangement provides comprehensive control over the channel from all sidewalls, achieving superior on-current and sub-threshold characteristics.
Solution Approach 2:
The gate electrode structure is nested around the channel in a wraparound configuration, with gate portions positioned at different vertical levels and lateral positions. This nested arrangement enables the gate to control electron flow from multiple directions simultaneously, achieving enhanced performance while maintaining a compact integrated form factor.
Data Source
AI summary
Dielectric wall structures are formed through a stack of a doped semiconductor material layer, a planar insulating spacer layer, and a sacrificial matrix layer. Gate electrode rails are formed through the dielectric wall structures and the sacrificial matrix layer. A two-dimensional array of rectangular openings is formed by removing remaining portions of the sacrificial matrix layer. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of rectangular openings. Gate dielectrics are formed on sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surround gates is formed, which may be employed as access transistors of a three-dimensional memory device.