Synchronous Rectifier Gate Timing for Leakage Inductance Commutation
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Solution Overview
Problem
Synchronous rectifier DC/DC converter power trains face inefficiencies due to commutation time caused by transformer leakage inductance, leading to increased energy loss and reliability issues, especially in low voltage outputs where the body diode's reverse recovery current and diode drop significantly impact efficiency.
Innovation Solution
The solution involves modifying the gate drive timing by introducing a non-zero overlap duration during transitions from high to low, where the second signal and its inverse are high, to compensate for transformer leakage inductance, thereby reducing the commutation time and associated losses. This is achieved by processing circuitry that generates and applies specific gate drive signals to transistors in a full-bridge synchronous rectifier configuration, ensuring optimal timing based on load current and transformer construction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed delays and logic are used to control MOSFETs, then the rectifier can be implemented with simple control circuitry, but current is forced to conduct through the body diode resulting in higher energy loss
Solution Approach 1:
The patent applies preliminary action by advancing the gate drive signal to the synchronous rectifier MOSFETs before the transformer leakage inductance would normally cause current to shift to the body diode. This proactive timing adjustment ensures the MOSFETs are already in the on-state when current commutation occurs, preventing body diode conduction and its associated energy losses while maintaining simple control circuitry
2Reliability
If complementary drive signals are used for full-bridge configuration, then reliability is improved by allowing single failure without interrupting output, but current must flow through two series devices doubling energy loss
Solution Approach 1:
The patent applies preliminary action by advancing the gate drive signals to both pairs of MOSFETs in the full-bridge configuration before current commutation occurs. This ensures both series-connected MOSFETs are in the low-resistance on-state during current flow, preventing body diode conduction in either device. The reliability benefit of the full-bridge configuration is maintained while eliminating the doubled energy loss that would occur with body diode conduction
3Device complexity
If gate drive timing does not compensate for leakage inductance, then circuit is simpler to implement, but commutation time causes current to flow through body diode reducing efficiency
Solution Approach 1:
The patent applies preliminary action by calculating and applying a timing advance to the gate drive signals based on the known transformer leakage inductance value. This compensation ensures that the MOSFETs are turned on before the leakage inductance would cause current commutation to the body diode, maintaining high efficiency. The timing compensation can be implemented with minimal additional circuitry by measuring leakage inductance and adjusting delay values
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power losses and enhances the reliability of the circuit by minimizing energy loss through the body diode, particularly at low voltage outputs, and prevents single faults from disrupting the power bus, while maintaining efficiency even in full-bridge configurations typically considered less efficient than half-bridge designs.
Implementation Method 1
synchronous rectifier gate drive timing to compensate for commutation time due to transformer leakage inductance
Data Source
AI summary
An apparatus for providing synchronous rectifier gate drive timing is described. The apparatus includes circuitry to receive a first signal. The apparatus also includes circuitry to generate a second signal by modifying the first signal to delay a transition from high to low for a non-zero overlap duration. An output to apply an inverse of the first signal as a gate drive timing of at least a first transistor and to apply the second signal as a gate drive timing of at least a second transistor, where the first transistor is a part of a primary side of a full-bridge synchronous rectifier and the second transistor is a part of a secondary side of the full-bridge synchronous rectifier is also included. The second signal and the inverse of the first signal are high during the overlap duration. Methods and program storage devices are also disclosed.