Rectifier Junction Structure for Higher Power Density in Small Chips
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Solution Overview
Problem
Existing rectifier diodes suffer from low power output, requiring larger chip sizes to generate sufficient power, which limits their efficiency in high power applications.
Innovation Solution
A high power density rectifier device is designed with a substrate silicon layer, a middle silicon layer, an upper silicon layer, and trench termination layers that increase the size of the p-n junction, allowing for higher power density while maintaining a smaller chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional rectifier diode structure is used, then manufacturing is simple, but power output is low
Solution Approach 1:
The patent transitions from a conventional planar p-n junction to a three-dimensional stacked structure with substrate silicon layer, middle silicon layer, and upper silicon layer. This vertical stacking increases the effective junction area and power density without proportionally increasing chip footprint, thereby resolving the contradiction between power output and device complexity.
Solution Approach 2:
The patent implements nested termination structures where first termination structures are formed in the substrate silicon layer and second termination structures are formed in the middle silicon layer. These nested termination regions confine the electric field and improve breakdown voltage without significantly increasing device complexity, enabling higher power output.
2Power
If larger chip size is used, then power output is sufficient, but chip area increases
Solution Approach 1:
By stacking multiple silicon layers vertically, the patent increases the effective power-generating area in the vertical dimension rather than expanding horizontally. This allows sufficient power output to be achieved on a smaller chip footprint, directly addressing the contradiction between power output and chip area.
Solution Approach 2:
The patent modifies the electrical parameters through doped regions and termination structures, increasing the breakdown voltage and power density. This enables higher power output per unit area, resolving the need for larger chip sizes to achieve sufficient power output.
3Productivity
If power density is increased, then efficiency improves, but device complexity increases
Solution Approach 1:
The patent divides the device into segmented functional regions: substrate silicon layer with first termination structures, middle silicon layer with second termination structures, and upper silicon layer. This segmentation allows each region to be optimized for specific functions (power generation, field confinement, contact), achieving high power density while managing complexity through modular design.
Solution Approach 2:
Different termination structures are applied locally in different layers: first termination structures in the substrate layer and second termination structures in the middle layer. This local differentiation optimizes the electric field distribution and breakdown characteristics in each region, enabling high power density without uniformly increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves increased power density and efficiency by forming a larger p-n junction through novel geometry, enabling higher power output without the need for larger chip sizes.
Implementation Method 1
A p-n junction may be formed between the upper silicon layer and the middle silicon layer
Data Source
AI summary
A high power density rectifier diode apparatus, structure and associated methods thereof. The apparatus includes a substrate silicon layer, a middle silicon layer coupled to the substrate layer, an upper silicon layer coupled to the middle silicon layer, a cathode terminal coupled to the substrate silicon layer, an anode terminal coupled to the upper silicon layer, and one or more trench termination layers formed in the substrate silicon layer and at least a portion of the middle silicon layer. The trench termination layers are configured to be formed on at least one side of the substrate silicon layer and at least a portion of the middle silicon layer. The substrate silicon layer is at least one of the following: an n-type layer, a p-type layer, and any combination thereof.