Rectilinear Macros with Non-Uniform Channel Spacing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SoC designs waste area by oversizing channel spacings to accommodate the maximum number of nets between macros, leading to inefficient use of integrated circuit space.
Innovation Solution
A floor planning technique that analyzes nets between macros to determine optimal channel spacing widths, allowing macros to be resized, reshaped, and repositioned to efficiently use area, with non-uniform channel spacings that adjust based on the number of nets, by extending or recessing macro facets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If channel spacing width is increased to accommodate the maximum number of nets between macros, then the number of nets that can be accommodated is improved, but the area of the integrated circuit increases due to wasted space
Solution Approach 1:
The patent applies local quality by varying the channel spacing width at different locations between macros. Instead of using a uniform channel spacing width across all regions, the channel spacing is locally adjusted to match the actual net requirements of each specific region. This allows the channel spacing to be wide only where needed to accommodate high-net-density regions, while being narrow in regions with fewer nets, thereby reducing overall area while maintaining the capability to accommodate the maximum number of nets where required.
Solution Approach 2:
The patent implements dynamics by making the channel spacing width adaptive rather than static. The floor planning technique dynamically determines optimal channel spacing widths based on the actual distribution and density of nets between macros. This dynamic approach allows the channel spacing to be optimized for each specific region's net requirements, preventing both over-provisioning (wasted area) and under-provisioning (insufficient net accommodation).
2Ease of manufacture
If uniform channel spacing width is used across all regions, then ease of manufacture is improved, but area efficiency deteriorates due to oversizing in low-net-density regions
Solution Approach 1:
The patent resolves this contradiction by applying local quality principles to the channel spacing design. The floor planning technique automatically determines different channel spacing widths for different regions based on local net density requirements. This maintains manufacturing ease by providing a systematic, automated approach to determining non-uniform spacing, while simultaneously improving area efficiency by avoiding uniform oversizing across the entire chip.
3Adaptability or versatility
If channel spacing is oversized to accommodate future net requirements, then adaptability is improved, but area is wasted in regions with current lower net density
Solution Approach 1:
The patent addresses this contradiction through dynamic adaptability. The floor planning technique creates a flexible channel spacing structure that can be easily adjusted as net requirements change. By using non-uniform channel spacing based on actual current net density, the design maintains adaptability - if future regions require more nets, the channel spacing can be locally increased without affecting other regions. This dynamic approach prevents permanent area waste while maintaining the capability to adapt to future requirements.
Data Source
AI summary
Circuits and methods for a system on a chip having non-uniform channel spacings is provided. In an example, a chip is provided that includes a first functional block having a rectilinear shape, the first processing unit having on a side a plurality of channel spacings. A first channel spacing of the plurality of channel spacings is positioned in contact with the side and a second functional block. A second channel spacing of the plurality of channel spacings is positioned in contact with the side and the second functional block. The width of the second channel spacing is non-uniform with the width of the first channel spacing.