Recursive Doubling DFE Circuit for Throughput Bottlenecks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing decision feedback equalizers (DFE) face limitations in throughput due to long computation times, with critical path delays scaling linearly with the number of symbols processed, limiting their performance in high-frequency operations.
Innovation Solution
Implementing a recursive doubling DFE circuit that reduces critical path delay to logarithmic or constant scaling with respect to the number of symbols processed, using loop-unrolled and pipelined architectures to enhance throughput without increasing clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional DFE processes multiple symbols sequentially, then computation accuracy is maintained, but throughput is limited due to linearly scaling critical path delay
Solution Approach 1:
The DFE computation is segmented into multiple independent processing stages, where each stage handles a portion of the symbol processing. This segmentation allows parallel execution of stages, reducing the overall critical path delay from linear to logarithmic scaling with the number of symbols processed.
Solution Approach 2:
The patent transitions from sequential one-dimensional processing to multi-dimensional parallel processing by organizing computations in a tree-like hierarchy. This dimensional change enables simultaneous processing of multiple symbols through spatial parallelism, achieving throughput proportional to the number of processing elements.
2Speed
If the clock frequency is increased to improve throughput, then processing speed increases, but critical path delay becomes prohibitively long
Solution Approach 1:
The critical path is segmented into multiple shorter stages that can be executed in parallel. By dividing the long sequential computation into smaller parallel tasks, the maximum path length is reduced, allowing higher clock frequencies without increasing overall complexity.
Solution Approach 2:
The patent employs dynamic clocking strategies where different processing stages can operate at different clock frequencies optimized for their specific computational requirements. This dynamic approach allows faster operation in critical paths while maintaining lower frequencies in less demanding stages.
3Productivity
If parallel processing is implemented to increase throughput, then computation time decreases, but circuit complexity increases
Solution Approach 1:
The patent implements a hierarchical nested structure where processing elements are organized in nested levels. Each level contains multiple instances of the previous level, creating a tree-like architecture. This nesting allows systematic scaling of parallelism while reusing computational blocks, managing circuit complexity through modular design.
Solution Approach 2:
The patent designs universal processing elements that can perform multiple functions depending on their position in the processing hierarchy. These multi-functional blocks reduce overall circuit complexity by eliminating the need for dedicated hardware for each specific computation type.
Data Source
AI summary
A circuit may include a first circuit, a second circuit, and a third circuit. The first circuit may generate a first set of channel state vectors corresponding to a communication channel, where each channel state vector in the first set of channel state vectors includes a set of channel state indices, and where each channel state index corresponds to a sequence of decoded symbols received over the communication channel. The second circuit may combine a first channel state vector and a second channel state vector in the first set of channel state vectors to obtain a combined channel state vector. The third circuit may select a first channel state index in the combined channel state vector based on a second channel state index.