Recursive IC Pin Mapping with Topological Refinement
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Solution Overview
Problem
Current interconnect routing solutions for IC package design face challenges in efficiently mapping thousands of pins across multiple substrate layers, failing to consider physical, electrical, and signal integrity rules, especially in high-pin-count packages with complex designs and multiple die components, leading to non-routable assignments that require significant manual refinement.
Innovation Solution
The solution involves recursive refinement of source and destination element mappings based on user-defined rules and priorities, using a topological map to optimize net assignments, and incorporating randomness to scan for better solutions, ensuring compliance with physical and electrical constraints while handling hierarchical net ordering and power/ground nets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automated routing is used for high pin count packages, then productivity is improved, but the complexity of establishing source-destination mappings increases significantly
Solution Approach 1:
The patent segments the pin mapping problem by organizing pins into hierarchical groups (e.g., functional blocks, modules, or regions) rather than treating all pins uniformly. This segmentation reduces the complexity of establishing source-destination mappings by breaking down the massive O(n*m) solution space into manageable subsets that can be processed independently and then combined.
Solution Approach 2:
The patent applies preliminary action by pre-establishing mapping rules, constraints, and priorities before the actual routing process begins. Source and destination pins are pre-categorized, pre-matched based on preliminary criteria, and pre-validated against design rules, which significantly reduces the computational complexity during the automated routing phase.
2Reliability
If comprehensive physical and electrical rules are enforced, then reliability is improved, but the time required for net assignment increases
Solution Approach 1:
The patent performs preliminary validation of source-destination mappings against physical and electrical rules before final routing assignment. By checking constraints early in the process and filtering out invalid mappings beforehand, the system ensures reliability without requiring extensive rework later, thus reducing overall assignment time.
Solution Approach 2:
The patent implements feedback mechanisms where the routing system continuously checks mappings against design rules and constraints, and automatically adjusts or rejects mappings that violate these rules. This feedback loop ensures that only compliant mappings proceed to routing, maintaining reliability while minimizing manual intervention time.
3Manufacturing precision
If manual refinement is performed on non-routable assignments, then solution quality is improved, but productivity decreases
Solution Approach 1:
The patent implements self-service by enabling the automated routing system to detect and correct its own mapping errors without requiring manual intervention. The system includes built-in validation, error detection, and automatic correction mechanisms that identify non-routable assignments and adjust them autonomously, maintaining high solution quality while preserving productivity.
Solution Approach 2:
The patent uses feedback loops where the routing system monitors assignment quality in real-time, identifies problematic mappings, and automatically refines them based on predefined criteria and constraints. This automated feedback and correction process eliminates the need for manual refinement, maintaining both high quality and productivity.
Data Source
AI summary
Aspects for optimized mapping of source elements to destination elements as interconnect routing assignments are described. The aspects include utilizing chosen rules to establish a priority for mapping, and generating mapping assignments based on the priority. The mapping assignments are recursively refined to converge on an optimized solution.