Recursive Metal-Embedded Chip Assembly Thermal Management

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Solution Overview

Problem

Current technologies face challenges in achieving effective thermal management for multi-scale and multi-chip integration, as wire bonds become too large for modern integrated circuits, hindering efficient coupling and interconnection between chips and components in large-scale packaging.

Innovation Solution

The recursive metal-embedded chip assembly (R-MECA) process, which involves embedding chips and heat spreaders on a carrier substrate, forming interconnects, and recursively integrating modules with embedded heat spreaders to achieve high-density and scalable thermal management across diverse device technologies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If wire bonds are used for chip interconnection, then chip coupling is achieved, but the wire bond size becomes too large for modern integrated circuits, making it difficult to couple ICs with pins or neighboring ICs

Engineering Contradiction:
Improvewire bond sizeVSAvoidcoupling difficulty
Core Design Contradiction:
Length of moving objectVSEase of operation

Solution Approach 1:

The patent extracts the interconnection function from traditional wire bonds and relocates it to the packaging substrate level. Through-substrate vias and trace interconnects are formed directly in the packaging substrate, eliminating the need for large wire bonds and enabling direct coupling between IC pins and neighboring ICs at the substrate level.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from planar wire bond interconnection to three-dimensional through-substrate vias. Conductive interconnects are formed by passing through the entire substrate thickness, enabling vertical and lateral connections simultaneously, thus reducing the horizontal space required for interconnections.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple chips are integrated in a single package, then integration density is improved, but thermal management becomes a major issue

Engineering Contradiction:
Improveintegration densityVSAvoidthermal management
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent merges the interconnection substrate with the heat spreader into a single integrated structure. The packaging substrate simultaneously provides electrical interconnection through through-substrate vias and thermal management through integrated heat spreaders, eliminating the need for separate thermal management components and enabling efficient heat dissipation in high-density multi-chip packages.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent employs composite material structures combining conductive materials for interconnection with thermally conductive materials for heat spreading. The packaging substrate integrates materials with different properties to simultaneously achieve electrical connectivity and thermal management functions in a unified structure.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables high-performance thermal management and scalable integration of heterogeneous devices, replacing wire bonding with embedded interconnects over heat spreaders, allowing for parallel processing and efficient integration of multiple chips at the wafer scale while addressing thermal issues in large-scale integration.

Implementation Method 1

U.S. Pat. No. 8,617,927 which is incorporated herein, teaches a method of mounting electronic dies or chips into an electroformed heat spreader offering an integrated solution to thermal management at the single-level wafer-scale integration

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

U.S. application Ser. No. 15/169,591, incorporated herein, addresses another important technology in connecting die to package using electroplated and suspended interconnects over integrated heat spreaders

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS10483184B1Recursive metal embedded chip assembly
Publication Date: 2019.11.19 HRL LAB
  • US10483184B1 patent drawing
  • US10483184B1 patent drawing
  • US10483184B1 patent drawing

AI summary

A recursive metal-embedded chip assembly (R-MECA) process and method is described for heterogeneous integration of multiple die from diverse device technologies. The recursive aspect of this integration technology enables integration of increasingly-complex subsystems while bridging different scales for devices, interconnects and components. Additionally, the proposed concepts include high thermal management performance that is maintained through the multiple recursive levels of R-MECA, which is a key requirement for high-performance heterogeneous integration of digital, analog mixed signal and RF subsystems. At the wafer-scale, chips from diverse technologies and different thicknesses are initially embedded in a metal heat spreader surrounded by a mesh wafer host. An embodiment uses metal embedding on the backside of the chips as a key differentiator for high-density integration, and built-in thermal management. After die embedding, wafer-level front side interconnects are fabricated to interconnect the various chips and with each other. The wafer is then diced into individual metal-embedded chip assembly (MECA) modules, and forms the level one for multi-scale R-MECA integration. These modules are subsequently integrated into another wafer or board using the same integration approach recursively. Additional components such as discrete passive resistors, capacitors and inductors can be integrated at the second level, once the high-resolution, high-density integration has been performed at level zero. This recursive integration offers a practical solution to build very large scale integrated systems and subsystems.