Recursive QAM Demodulator for Lower-Complexity High-Order Signals
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Solution Overview
Problem
Existing wireless communication systems face challenges in demodulating high-order QAM signals without excessive hardware complexity and power consumption, particularly in MIMO systems where the number of comparators and reference values required increases exponentially with modulation order.
Innovation Solution
A QAM demodulator with a recursive structure that utilizes constellation characteristics to reduce hardware complexity and power consumption by employing a first calculation circuit to derive I and Q components, followed by a series of comparators and summers to sequentially output bits, and a sub-QAM demodulator to process remaining bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional QAM demodulation is used for high-order modulation, then demodulation capability is improved, but hardware complexity increases exponentially
Solution Approach 1:
The patent divides the bit stream into multiple groups and processes each group separately through parallel demodulation paths. Each path handles a subset of bits using reduced-complexity comparators and reference value sets, transforming a single complex demodulation task into multiple simpler parallel tasks that collectively achieve high-order QAM demodulation without exponential hardware growth
Solution Approach 2:
The patent implements a hierarchical structure where a main demodulation framework contains multiple sub-demodulation paths. Each sub-path processes specific bit groups using nested comparison logic and reference value sets, with the overall structure allowing high-order modulation support while maintaining manageable complexity at each nesting level through systematic reuse of computational building blocks
2Adaptability or versatility
If conventional QAM demodulation is used for high-order modulation, then demodulation capability is improved, but power consumption increases
Solution Approach 1:
The patent segments the demodulation workload into parallel paths that each process subsets of bits with reduced computational requirements. By distributing the processing load across multiple simpler units rather than using a single complex unit, the patent reduces overall power consumption while maintaining the capability to handle high-order modulation through coordinated operation of these segmented processing elements
Solution Approach 2:
The patent changes the operational parameters of the demodulation process by using different reference value sets and comparison thresholds for different bit groups. This parameter variation allows each processing path to operate more efficiently with lower power requirements, while the collective operation of all paths maintains high-order modulation demodulation capability
3Measurement precision
If the number of comparators is increased to support high-order QAM, then demodulation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the comparator functions into multiple specialized comparison units, each handling specific bit groups with tailored reference values. This segmentation maintains demodulation accuracy by ensuring each comparator unit is optimized for its specific task, while avoiding the need for a single large-scale comparator system that would dramatically increase device complexity
Solution Approach 2:
The patent designs comparator units and reference value sets that can be universally applied across multiple processing paths. Each comparator unit serves multiple functions by processing different bit groups through systematic reuse of the same hardware structure with reconfigurable reference values, thereby maintaining high demodulation accuracy without proportionally increasing device complexity
Data Source
AI summary
A QAM demodulator including a first calculation circuit including a real part returning circuit and an imaginary part returning circuit that derive, from a first complex symbol, an in phase (I) component and a quadrature phase (Q) component, respectively; first and second comparators for receiving the I and Q components, and based thereon, outputting respective bits of a bit string; first and second absolute value returning circuits that derive absolute values of the I and Q components (“abs(I)” and “abs(Q)”); first and second summers to sum each of abs(I) and abs(Q) with a first reference value and thereby provide first and second summed outputs; and a sub-QAM demodulator configured to QAM demodulate a second complex symbol and thereby output corresponding bits. I and Q components of the second complex symbol are based on the first and second summed outputs. The corresponding bits are remaining bits of the bit stream.