Recursive Signal Network for Parallel Computing

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Solution Overview

Problem

Current massively parallel computing systems face challenges in efficiently organizing and scheduling concurrent tasks across multiple digital computing engines, leading to complexities in task interactions and intercommunication, particularly due to the need for extensive interconnecting paths and specialized programming techniques, which limits their scalability and reliability.

Innovation Solution

A data-processing connectivity system featuring a recursive network of signalling paths and pivot nodes that enable bidirectional communication between digital computing engines, allowing for concurrent array processing and efficient data transmission through a hierarchical structure, with each node having autonomous control over its scope and interconnected cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple digital computing engines are interconnected to execute tasks simultaneously, then productivity is improved through parallel processing, but device complexity increases due to extensive interconnecting paths and task synchronization requirements

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidinterconnecting paths complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system segments the massively parallel computing task into two distinct layers: a control plane for task distribution and scheduling, and a data plane for actual computation. This segmentation allows the complex interconnecting paths to be organized into manageable routing domains, where each domain handles specific task flows independently, reducing overall system complexity while maintaining high productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces specialized intermediary components including routing nodes that manage task distribution, scheduling entities that coordinate computation workflows, and buffer memory structures that mediate data flow between computing engines. These intermediaries absorb the complexity of interconnections, providing standardized interfaces that simplify the overall system architecture while enabling efficient parallel processing.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If digital computing engines operate independently with minimal intercommunication, then device complexity is reduced, but adaptability decreases due to limited task coordination capability

Engineering Contradiction:
Improvetask synchronization complexityVSAvoidtask coordination capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The system implements dynamic task scheduling and routing mechanisms that adapt computation workflows in real-time based on engine availability, task priorities, and system state. Computing engines can dynamically join or leave computation groups, and task routes are dynamically rerouted around busy or failed engines, providing high adaptability without requiring complex permanent synchronization structures between all engines.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent creates universal communication protocols and standardized interface structures that enable computing engines to perform multiple functions including computation, data storage, task routing, and error handling. This multi-functionality allows engines to adapt to different task requirements without requiring specialized complex interconnection structures, maintaining simplicity while enhancing versatility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If extensive interconnecting paths are provided between digital computing engines, then adaptability is improved for diverse task coordination, but device complexity and reliability worsen due to increased failure points

Engineering Contradiction:
Improvetask interaction flexibilityVSAvoidsystem reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system implements local quality by creating specialized routing domains and communication sub-networks optimized for specific task types and engine groups. Each domain has tailored error handling and routing logic that improves reliability for local operations, while the hierarchical structure prevents local failures from propagating system-wide, maintaining overall system reliability despite extensive interconnections.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent incorporates beforehand cushioning through buffer memory structures, error detection and correction codes in communication protocols, and redundant routing paths that are pre-configured for failover. These protective measures are built into the interconnecting paths before failures occur, allowing the system to maintain reliability even with extensive connections by preventing and mitigating failure propagation.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

4Productivity

If specialized programming techniques are required for parallel task management, then productivity is improved through efficient resource utilization, but ease of operation worsens due to programming complexity

Engineering Contradiction:
Improveresource utilization efficiencyVSAvoidprogramming simplicity
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The system implements self-service through automatic task distribution, dynamic resource allocation, and autonomous scheduling mechanisms that eliminate the need for manual programming of parallel task coordination. The routing nodes and scheduling entities automatically manage task assignment and resource utilization, providing high productivity through efficient resource usage while maintaining programming simplicity by abstracting away complex parallel management details from the user.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11016930B2Digital processing connectivity
Publication Date: 2021.05.25 HAMLIN DERRICK JOHN
  • US11016930B2 patent drawing
  • US11016930B2 patent drawing
  • US11016930B2 patent drawing

AI summary

A connectivity has a first network (25) of signal-links interconnecting a large plurality of address-bearing, computing cells (20 and 22). Some of the links are selectable according to addresses hierarchically ordered along a recursive curve. Most of the address-designated links that form the network are switchably operable between cells such that a first selectable set of cells along one segment of the recursive curve form signal-routes to a second selectable set of cells, along a second segment. For receipt of instructions and for synchronisation, some segments have a switchable signal-path from one controlling cell of that segment. A second network (23) has signal-links interconnecting a plurality of processing cells (19 and 21) some of which control the loading of data into cells of the first network. The computing and processing cells have pairwise matching of addresses and are pairwise coterminous, which ensures that control of the connectivity by second network (23) is directed to localisably-selectable segments of first network (25).