Recursive ZQ Calibration for Precise Memory Driver Impedance

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Solution Overview

Problem

Conventional impedance calibration methods for semiconductor memory devices often result in inconsistent resistance values due to nonlinear characteristics of data drivers, leading to signal distortion as operating speeds increase.

Innovation Solution

A semiconductor memory device and method that performs recursive impedance calibration using an external resistor and an on-chip dummy pull-down driver, generating precise impedance codes without binary operations, adjusting resistance values through recursive code generation and calibration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If binary multiplication is applied to the ZQ code to implement the target resistance value, then the impedance calibration operation can be performed, but the resistance value set due to the nonlinear characteristics of the actual data driver is inconsistent with the actual target resistance value

Engineering Contradiction:
Improveimpedance calibration precisionVSAvoidresistance value consistency
Core Design Contradiction:
Measurement precisionVSManufacturing precision

Solution Approach 1:

The impedance calibration process is divided into multiple recursive steps where the calibration range is segmented into smaller intervals. In each step, the calibration resolution is doubled by adjusting the reference resistance to half of the previous step's reference resistance, allowing progressive refinement of the resistance value to match the target precision without relying on binary multiplication that causes inconsistency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The reference resistance value is dynamically adjusted during the calibration process. Instead of using a fixed reference resistance, the system recursively updates the reference resistance to half of its previous value in each calibration step, enabling adaptive precision improvement. This dynamic adjustment allows the calibration to converge to the target resistance value while compensating for nonlinear characteristics of the data driver.

Inventive Principle:
Principle #15Dynamics

2Speed

If the operating speed of the semiconductor memory device is increased, then the performance is improved, but the signal distortion due to impedance mismatch becomes more severe

Engineering Contradiction:
Improveoperating speedVSAvoidsignal integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The impedance calibration circuit uses feedback from the actual voltage division ratio to adjust the calibration code. By monitoring the actual resistance value and comparing it with the target value, the system recursively refines the calibration code to eliminate impedance mismatch. This feedback mechanism ensures that even at high operating speeds, the impedance matching remains accurate, preventing signal distortion and maintaining signal integrity.

Inventive Principle:
Principle #23Feedback

3Ease of manufacture

If conventional impedance calibration is performed using external resistor only, then the calibration process is simple, but the calibration precision is insufficient for high-speed operations

Engineering Contradiction:
Improvecalibration process simplicityVSAvoidcalibration precision
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The calibration system uses a nested structure where an on-chip dummy pull-down driver is integrated within the calibration circuit. This dummy driver acts as a variable resistance element that can be controlled through code adjustment. The nesting of this controllable resistance within the calibration circuit allows for programmable precision improvement while maintaining a compact structure that does not significantly increase manufacturing complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS12483243B2Semiconductor memory device performing recursive ZQ calibration and calibration method thereof
Publication Date: 2025.11.25 SAMSUNG ELECTRONICS CO LTD
  • US12483243B2 patent drawing
  • US12483243B2 patent drawing
  • US12483243B2 patent drawing

AI summary

A semiconductor memory device may include an impedance adjustment pad, a dummy pull-down driver and an external resistor connected in parallel between the impedance adjustment pad and a ground, a recursive code generation circuit configured to recursively generate a pull-up code and a pull-down code corresponding to a target resistance by using the external resistor and the dummy pull-down driver as a reference resistance, in an impedance calibration operation of the semiconductor memory device, a code register configured to store the generated pull-up code and the pull-down code, and a calibration control logic circuit configured to control the recursive code generation circuit during a plurality of steps in the impedance calibration operation while adjusting a resistance value of the dummy pull-down driver.