Recycled Fine-Granularity RAS Chain for Memory Timing Control
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Solution Overview
Problem
Existing counter-based RAS chains in memory devices suffer from limited timing granularity and area efficiency, making it difficult to adjust trim ranges and reorder signals effectively.
Innovation Solution
A counter-based RAS chain with Match and Delay blocks that utilize a Gray code counter and configurable delay chain to provide fine timing granularity and improve area efficiency, allowing for flexible programming of timing control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a counter-based RAS chain is used to provide timing control signals, then the ability to program event timings and reorder events is improved, but the timing granularity is limited due to oscillator timing granularity and Gray code counter delay
Solution Approach 1:
The patent divides the timing control function into two independent counters: a coarse counter that provides the base timing granularity and a fine counter that adds fine-grained timing adjustments. This segmentation allows the system to achieve both programming flexibility and fine timing granularity by combining the outputs of the two counters, overcoming the limitation of using a single counter with fixed granularity.
Solution Approach 2:
The patent introduces an additional dimension to the timing control by adding a fine counter that operates in parallel with the coarse counter. This creates a two-dimensional timing space where the coarse counter provides the primary timing scale and the fine counter provides the secondary, finer scale, enabling precise timing control without being constrained by the oscillator's fixed granularity.
2Adaptability or versatility
If delay elements are added or removed to adjust the trim range in a delay-based RAS chain, then the timing adjustment range is improved, but the area efficiency deteriorates
Solution Approach 1:
The patent implements dynamic timing adjustment through programmable counters that can be configured via control signals. Instead of physically adding or removing delay elements to change the trim range, the system dynamically reconfigures the counter values and timing parameters through digital control, achieving wide timing adjustment range without increasing physical area.
Solution Approach 2:
The patent changes the timing parameters through digital programming of the counters rather than physical modification of the circuit structure. By adjusting the counter values, prescaler divisions, and event timing registers through control signals, the system achieves flexible trim range adjustment without adding physical delay elements, thereby maintaining area efficiency.
3Measurement precision
If the timing granularity of the oscillator is increased to improve fine timing control, then the timing precision is improved, but the device complexity increases
Solution Approach 1:
The patent segments the timing precision function into two parts: a coarse timing component provided by the existing oscillator and counter, and a fine timing component provided by the fine counter. This segmentation allows the system to achieve high timing precision without requiring the oscillator itself to have ultra-fine granularity, thereby avoiding the complexity increase that would result from redesigning the oscillator.
Solution Approach 2:
The fine counter acts as an intermediary between the coarse oscillator timing and the required fine timing precision. Instead of modifying the oscillator to provide fine timing directly, the fine counter mediates by adding incremental timing adjustments to the coarse oscillator pulses, achieving high precision output without the complexity of a high-granularity oscillator.
Data Source
AI summary
Systems and methods are provided for generating timing control signals for controlling the access to the memory cells of a memory device. The memory device employs a counter-based RAS chain circuit including multiple Match and Delay blocks to generate timing control signals with fine timing granularities. The Match and Delay blocks include circuits to enable area savings and improve area efficiency (AE) in the memory device as well as improve the flexibility for development chips and production parts.