Recyclic Pipelined ADC Architecture for Higher Bit Resolution
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Solution Overview
Problem
Pipelined analog-to-digital converters face limitations in resolving a larger number of bits due to flash/comparator offset, which restricts closed-loop residue gain and increases noise contribution, especially in the first stage, affecting Spurious-Free Dynamic Range (SFDR).
Innovation Solution
A recyclic pipeline architecture with a sample switch, sampling capacitor, amplifier, feedback branches, and hold switches, including N-bit and M-bit converter pairs, and capacitors with specific capacitance ratios, allowing for increased closed-loop gain and reduced noise contribution through staged conversion and feedback paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the first stage resolves a larger number of bits, then the total number of stages is reduced and power consumption is lowered, but flash/comparator offset limits the number of bits that can be resolved
Solution Approach 1:
The first stage is segmented into two independent converter pairs (N-bit and M-bit), each handling a portion of the bit resolution. This segmentation allows each converter pair to operate with reduced offset constraints while collectively achieving higher resolution, overcoming the limitation of a single large-bit flash/comparator stage.
Solution Approach 2:
The patent introduces a new architectural dimension by implementing multiple parallel converter pairs with different bit resolutions (N-bit and M-bit) that process signals simultaneously. This multi-dimensional approach to bit resolution allows the system to achieve high precision without being constrained by the offset limitations of a single conventional flash/comparator stage.
2Measurement precision
If the first stage resolves more bits, then fewer stages are needed, but the closed loop residue gain is limited which increases noise contribution
Solution Approach 1:
Each converter pair is equipped with feedback mechanisms that allow the system to compensate for noise and maintain high closed-loop residue gain. The feedback paths enable the amplifiers to operate with optimal gain settings while the converter pairs handle the bit resolution, thereby reducing noise contribution even as bit resolution increases.
Solution Approach 2:
The patent changes the operational parameters of the converter pairs by using different bit resolutions (N-bit and M-bit) and adjusting their respective weights and feedback factors. This parameter optimization allows each converter pair to contribute maximally to the overall precision while minimizing noise, enabling higher total bit resolution without increasing noise contribution.
3Measurement precision
If conventional single-stage designs are used, then device complexity is lower, but Spurious-Free Dynamic Range is limited
Solution Approach 1:
The ADC is segmented into multiple parallel converter pairs, each with simplified individual architecture but collectively achieving high SFDR. This segmentation allows each unit to be less complex while the combined system achieves superior dynamic range performance.
Solution Approach 2:
Multiple converter pairs with different bit resolutions are merged in parallel, combining their individual outputs to achieve high Spurious-Free Dynamic Range. The merging of these simpler units creates a system with performance exceeding what a single complex converter could achieve.
Data Source
AI summary
An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.