Redistributed Chip Packaging Thermal Contact Device Backside
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Solution Overview
Problem
Conventional integrated circuit packaging technologies face limitations in heat dissipation, particularly in high-power devices, due to thermal bottlenecks caused by interconnect layers, which restrict the efficiency of thermal energy dissipation.
Innovation Solution
The proposed solution involves an integrated circuit assembly with a panel encapsulating a power amplifier or semiconductor device, featuring thermally and electrically conductive panel vias and a thermal slab for enhanced heat dissipation, along with interconnect layers that eliminate wirebonds, allowing for improved thermal and electrical paths to ground.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wirebond modules with HDI layers are used, then electrical interconnection is achieved, but heat dissipation is limited due to thermal bottleneck through HDI layers
Solution Approach 1:
The patent introduces a third dimension for heat dissipation by adding a thermal path through the substrate backside, complementing the conventional topside heat dissipation path. This dimensional addition allows heat to escape through multiple routes simultaneously, bypassing the thermal bottleneck of HDI layers.
Solution Approach 2:
The patent introduces a thermal interface material as an intermediary between the device backside and the heat sink. This intermediary optimizes thermal transfer by filling gaps and improving contact, thereby enhancing heat dissipation efficiency without requiring direct metal-to-metal contact.
2Productivity
If RCP with die down configuration is used, then packaging density is improved by eliminating wirebonds, but heat dissipation is bottlenecked by interconnect layers
Solution Approach 1:
The patent segments the heat dissipation function into two independent paths: one through the interconnect layers at the topside and another through the substrate backside to a heat sink. This segmentation allows the electrical interconnect structure to maintain high density while the thermal management function is handled separately through the substrate.
Solution Approach 2:
The substrate is given dual functionality: it serves both as the mechanical support structure for the die and interconnect layers, and as a thermal conduction path to the heat sink. This multi-functionality eliminates the need for separate wirebonds (maintaining density) while enabling effective heat dissipation through the backside path.
3Temperature
If heat spreader is used with RCP, then some thermal management is improved, but interconnect layers still present heat dissipation bottleneck
Solution Approach 1:
The patent adds a vertical thermal path through the substrate backside, creating a third dimension for heat flow that is independent of the horizontal interconnect layer path. This dimensional addition bypasses the bottleneck created by interconnect layers and allows direct thermal coupling between the device and heat sink.
4Power
If conventional packaging is used for high-power devices, then device functionality is achieved, but thermal energy dissipation is insufficient
Solution Approach 1:
The patent applies localized thermal management by creating a dedicated thermal conduction path specifically at the device backside region. The thermal interface material and heat sink are positioned to provide focused cooling exactly where the highest thermal loads are generated, rather than relying on general packaging-level thermal management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces junction temperatures, enabling more efficient thermal management and integration benefits for high-power devices, with thermal modeling indicating junction temperatures below 150°C, surpassing conventional RCP solutions.
Implementation Method 1
A lower surface of the panel is in thermal contact with either the circuit board or a thermal slab
Implementation Method 2
The panel includes a set of panel vias that are thermally and electrically conductive
Data Source
AI summary
An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.