Redistributed Metal Interconnection for Stable Power Supply
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Solution Overview
Problem
The challenge in semiconductor chip packaging is to reduce dimensions while maintaining high-performance requirements, particularly in providing stable power and ground voltage supply to internal circuits, which existing technologies struggle to achieve due to limitations in redistributing metal interconnections effectively.
Innovation Solution
The solution involves creating semiconductor chips with redistributed metal interconnections that directly connect internal power and ground lines to chip pads through via-holes and openings in a passivation layer, using low-resistivity copper layers and additional metal layers for improved adhesion and oxidation prevention, thereby providing additional stable voltage supply paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional metal interconnection structures are used, then the chip package dimensions can be reduced, but the stability of power and ground voltage supply to internal circuits deteriorates
Solution Approach 1:
The patent introduces a redistributed metal interconnection layer positioned between the chip pad and the internal circuit, adding a dimensional layer to the interconnection structure. This redistributed layer provides additional parallel paths for power and ground signals, reducing electrical resistance and improving voltage stability without increasing the overall chip package footprint.
Solution Approach 2:
The patent segments the power and ground interconnections into multiple separate metal layers and distributed via-holes rather than using a single continuous trace. This segmentation creates multiple parallel conduction paths, reducing the overall electrical resistance and providing better power delivery to the internal circuit while maintaining compact dimensions.
2Reliability
If additional metal interconnection layers are added to improve power supply stability, then the electrical resistance decreases, but the device complexity increases
Solution Approach 1:
The redistributed metal interconnection layer serves multiple functions simultaneously: it provides additional parallel paths for power and ground signals, acts as a shielding layer to reduce parasitic capacitance between signal lines and reference planes, and provides mechanical support structure. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent merges the power delivery function with the structural and shielding functions into a single redistributed metal layer system. By combining these functions, the patent achieves improved power supply stability without proportionally increasing the number of separate components or processing steps required.
Data Source
AI summary
Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.