Redistribution Structure Barrier Layers for Reliable Semiconductor Packaging
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Solution Overview
Problem
The mechanical and electrical reliability of semiconductor packages with redistribution structures is a concern due to the increasing integration of chips, which requires improved insulation and connectivity between redistribution layers and insulating layers.
Innovation Solution
A semiconductor package design featuring a redistribution structure with stacked redistribution layers, insulating layers, and self-forming barrier layers that prevent metal diffusion and enhance adhesion between layers, improving mechanical and electrical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chip integration is improved and chip size is reduced, then device miniaturization and integration density are enhanced, but mechanical and electrical reliability of the redistribution structure deteriorates
Solution Approach 1:
The redistribution structure is divided into multiple redistribution layers (first, second, third redistribution layers) separated by redistribution insulating layers. This segmentation allows each layer to be optimized independently for mechanical strength and electrical connectivity, maintaining reliability while achieving higher integration density through vertical stacking.
Solution Approach 2:
The patent employs composite material structures including barrier layers made of different materials (e.g., tungsten, tantalum) combined with redistribution layers and insulating layers. These composite structures provide both mechanical support and electrical isolation, enhancing overall reliability while enabling miniaturization through efficient space utilization.
2Productivity
If redistribution layers are stacked in vertical direction to increase integration, then connection density is improved, but adhesion between layers and prevention of metal diffusion becomes more difficult
Solution Approach 1:
Redistribution insulating layers are introduced as intermediary materials between adjacent redistribution layers. These insulating layers prevent direct contact between metal layers, thereby preventing metal diffusion while maintaining electrical connectivity through controlled via structures. The insulating layers also provide adhesion promotion between stacked layers.
Solution Approach 2:
Barrier layers are formed through self-aligned processes where the barrier material automatically positions itself at the interfaces between metal and insulator layers. This self-service approach ensures precise placement for diffusion prevention without requiring additional alignment steps, maintaining manufacturing precision while enabling vertical stacking.
3Reliability
If barrier layers are formed to prevent metal diffusion, then electrical insulation and reliability are improved, but manufacturing complexity and process steps increase
Solution Approach 1:
The barrier layer formation process is merged with the existing redistribution layer fabrication process. The same patterning and deposition tools used for creating redistribution layers are utilized to form barrier layers, combining multiple functions into a single integrated process flow. This reduces manufacturing complexity while maintaining electrical insulation reliability.
Solution Approach 2:
Barrier layers are formed preliminarily before the redistribution layers are fully constructed. By pre-positioning the barrier material at the interfaces, the subsequent deposition of metal layers occurs with built-in diffusion protection already in place. This preliminary action simplifies the overall manufacturing sequence while ensuring reliable electrical insulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the mechanical and electrical reliability of semiconductor packages by preventing metal diffusion and improving adhesion between redistribution layers and insulating layers, ensuring stable chip connections and performance.
Implementation Method 1
a plurality of self-formed barrier layers formed between side surfaces of the plurality of redistribution layers and the plurality of redistribution insulating layers
Implementation Method 2
improving adhesion between redistribution layers and insulating layers
Data Source
AI summary
A semiconductor package includes a first redistribution structure including a top surface, a chip arranged on the top surface of the first redistribution structure the chip having a top surface, bottom surface, and side surfaces, and a package body arranged on the top surface of the first redistribution structure to cover the side surfaces of the chip. The first redistribution structure includes a plurality of redistribution layers stacked in a vertical direction, a plurality of redistribution insulating layers stacked in the vertical direction and which insulate the plurality of redistribution layers from each other, a plurality of redistribution vias buried in a plurality of redistribution via holes penetrating the plurality of redistribution insulating layers and electrically connecting the plurality of redistribution layers to each other, and a plurality of self-formed barrier layers formed between side surfaces of the plurality of redistribution layers and the plurality of redistribution insulating layers.