Redistribution Bridge Layout for Multi-Die Cache and Logic Integration
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Solution Overview
Problem
Challenges arise during the scaling-down process of semiconductor devices, impacting quality, yield, performance, and reliability, with increasing complexity.
Innovation Solution
A semiconductor device design featuring a first die with a redistribution structure, a second die with a cache unit, and a third die with a cache unit, connected via conductive layers and bridge layers, allowing cooperative operation and independent access to the first die, enhancing performance and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If semiconductor devices are scaled down to meet increasing computing demand, then computing ability is improved, but quality, yield, performance, and reliability deteriorate with increasing complexity
Solution Approach 1:
The semiconductor device is divided into multiple separate dies (first die, second die, third die) with distinct functions. The first die contains cache memory while the second and third dies contain logic units. This segmentation allows each die to be optimized independently for its specific function, improving overall reliability and yield while maintaining high computing performance through parallel operation.
2Power
If multiple cache units are added to enhance performance, then computing ability is improved, but device complexity increases
Solution Approach 1:
Instead of adding cache units in the same plane which会增加 complexity, the invention uses vertical stacking with redistribution structures. The first redistribution structure is positioned between the first die and the second/third dies, creating a three-dimensional arrangement. This dimensional transition allows multiple cache units to be accessed efficiently without proportionally increasing planar complexity.
3Productivity
If smaller dies are used to improve yield, then manufacturing yield is improved, but maintaining access to cache memory becomes more difficult
Solution Approach 1:
The first redistribution structure serves as an intermediary between the first die (cache memory) and the second and third dies (logic units). This redistribution structure includes conductive layers that efficiently route signals between the cache memory on the first die and the logic units on the second and third dies, maintaining easy cache access despite the use of smaller, separately fabricated dies.
Data Source
AI summary
The present application provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and comprising a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and comprising a second cache unit. The first redistribution structure comprises: a plurality of conductive layers electrically coupled the first die and the first cache unit of the second die and electrically coupled the first die and the second cache unit of the third die, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit of the second die and the second cache unit of the third die are topographically aligned with the first die. The first die is configured as a cache memory, and the second die and the third die are configured as logic dies.