Redistribution Chip for Stacked Semiconductor Electrode Alignment
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Solution Overview
Problem
The challenge in stacking semiconductor chips of different planar sizes is the limitation it imposes on design freedom and efficient signal transmission due to the need for precise electrode layout and through silicon via placement, which complicates manufacturing and reduces the ability to downsize the package while maintaining high signal transmission rates.
Innovation Solution
A semiconductor device configuration where a redistribution chip with lead wirings is used to adjust the electrode positions, allowing for overlapping through silicon vias and electrodes between chips, enabling efficient electrical connections without bonding wires and reducing impedance, thus improving design freedom and signal transmission reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If through silicon vias are used to electrically connect stacked semiconductor chips, then transmission distance is reduced and signal transmission rate is improved, but design freedom is limited due to the need for precise electrode layout and via placement
Solution Approach 1:
A redistribution chip is introduced as an intermediary component between the first and third semiconductor chips. This redistribution chip includes through silicon vias and lead wirings that serve as mediators to electrically connect the chips. By placing the redistribution chip in the middle, the design allows flexible electrode layouts on the first and third chips without requiring precise alignment, thus maintaining high signal transmission rates while improving design freedom.
2Volume of moving object
If multiple semiconductor chips of different planar sizes are stacked, then package size can be reduced, but manufacturing complexity increases due to alignment requirements
Solution Approach 1:
The redistribution chip acts as a mediator that simplifies the stacking process. It includes a substrate with through silicon vias and lead wirings that can be independently routed, allowing the first and third semiconductor chips to be connected without requiring precise alignment between their electrodes. This intermediary structure reduces manufacturing complexity while enabling compact packaging of chips with different planar sizes.
Solution Approach 2:
The invention transitions from planar electrode alignment to three-dimensional connectivity through the redistribution chip. The through silicon vias extend in the vertical dimension, allowing electrical connections to be established without requiring precise horizontal alignment between chips. This dimensional change simplifies the stacking process and reduces manufacturing complexity.
3Adaptability or versatility
If wire bonds are used for electrical connection, then design flexibility is maintained, but transmission distance increases and signal transmission rate decreases
Solution Approach 1:
The invention replaces the mechanical wire bonding system with a direct electrical connection system using through silicon vias and lead wirings. This substitution eliminates the need for physical wire bonds, reducing transmission distance and improving signal transmission rates while maintaining design flexibility through the redistribution chip's flexible electrode and via layout.
Data Source
AI summary
A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board. The logic chip and the memory chip are electrically connected via the redistribution chip. The redistribution chip includes a plurality of front surface electrodes formed to a front surface facing the wiring board, and a plurality of back surface electrodes formed to a back surface opposite to the surface. The redistribution chip has a plurality of through silicon vias, and a plurality of lead wirings formed to the front surface or the back surface and electrically connecting the plurality of through silicon vias and the front surface electrodes or the back surface electrodes.