Redistribution Circuit Structure Alignment Mark Fabrication
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently forming redistribution circuit structures for integrated fan-out packages, particularly in achieving compactness and high integration density, which requires precise fabrication of conductive vias and alignment marks to ensure effective electrical connectivity and packaging efficiency.
Innovation Solution
A method involving the formation of conductive pillars and protection layers on integrated circuits, followed by the creation of insulating encapsulations and redistribution circuit structures through multi-step plating processes, including the use of polybenzoxazole layers and chemical mechanical polishing, to achieve precise alignment and electrical connectivity, enabling compact and efficient packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-step plating processes are used to form conductive vias and alignment marks, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The fabrication process is divided into multiple sequential plating steps (first plating step, second plating step, third plating step), where each step forms specific features (conductive vias, alignment marks, conductive pillars) with controlled parameters. This segmentation allows precise control over the geometry and material properties of each feature while maintaining overall process manageability.
Solution Approach 2:
Different regions of the substrate receive different treatments through selective plating. The first conductive vias, second conductive vias, alignment marks, and conductive pillars are formed with locally optimized plating parameters (current density, agitation, duration) to achieve the specific dimensional and material requirements of each feature type.
2Productivity
If feature size is reduced to increase integration density, then productivity is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The plating parameters (current density, agitation intensity, plating duration, temperature) are systematically adjusted between different plating steps to control the dimensional characteristics of features at reduced scales. For example, lower current density and reduced agitation in later steps enable precise formation of smaller conductive pillars and alignment marks while maintaining manufacturing control.
3Productivity
If aggressive plating conditions are used to increase plating speed, then productivity is improved, but manufacturing precision deteriorates due to damage to conductive layers and alignment marks
Solution Approach 1:
The plating process uses periodic alternation between high-speed plating steps and low-speed precision plating steps. Aggressive plating conditions (high current density, strong agitation) are applied only when forming robust features like conductive vias, while gentler conditions are used for precision features like alignment marks and conductive pillars, thereby protecting feature integrity while maintaining overall productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of redistribution circuit structures with high lithography resolution and short signal transmission paths, enhancing packaging efficiency and yield while minimizing damage to conductive layers and alignment marks, thereby supporting the development of compact and high-density semiconductor packages.
Implementation Method 1
A multi-step plating process is performed to form a patterned conductive layer on the seed layer exposed by the opening and the at least one trench
Implementation Method 2
chemical mechanical polishing, to achieve precise alignment and electrical connectivity
Data Source
AI summary
A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.