Redistribution Circuit Build-Up for Precise Wafer-Level Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current wafer level packaging technologies face challenges in efficiently integrating semiconductor dies and forming reliable redistribution circuit structures, particularly in achieving precise alignment and robust electrical connections.
Innovation Solution
The proposed method involves forming a redistribution circuit structure on a carrier with a debond layer, encapsulating semiconductor dies, and planarizing the encapsulation to expose the dies and vias. This is followed by forming multiple seed layers and patterned conductive layers, with dielectric layers in between, to create a multi-layer build-up structure that enhances electrical connectivity and mechanical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer level packaging is used to integrate semiconductor dies, then productivity is improved, but manufacturing precision deteriorates due to challenges in achieving precise alignment and robust electrical connections
Solution Approach 1:
The patent applies preliminary action by forming a debond layer on the carrier before mounting the semiconductor wafer, and by pre-forming the redistribution circuit structure on the carrier. This allows for better alignment control and electrical connection establishment before the actual die integration process, thereby improving manufacturing precision while maintaining high productivity through wafer-level processing
2Reliability
If multiple seed layers and conductive layers are formed to create multi-layer build-up structure, then reliability of electrical connections is improved, but device complexity increases
Solution Approach 1:
The patent segments the electrical connection structure into multiple functional layers: debond layer, conductive layers, dielectric layers, and seed layers. Each layer performs a specific function (adhesion, electrical conduction, insulation, or structural support), which improves overall connection reliability while making the complex structure more manageable through functional decomposition
3Ease of operation
If semiconductor dies are encapsulated and planarized to expose dies and vias, then ease of operation is improved for subsequent processing, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces an encapsulation layer as an intermediary that protects the semiconductor dies and underlying structures during processing, while controlled planarization selectively exposes the dies and vias. The debond layer serves as another intermediary that facilitates the separation and exposure process, making subsequent operations easier while managing the precision requirements through these intermediate structures
Data Source
AI summary
A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.