Redistribution Structure With Dummy Bump Region for CTE Strain Relief
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Solution Overview
Problem
The difference in coefficient of thermal expansion (CTE) values between substrates and components in chip packages leads to deformation, causing strain concentration and potential breaks in electrical connections within the redistribution structure, rendering the chip package inoperable.
Innovation Solution
A dummy bump region (DBR) with enhanced vias and wiring interconnects is formed between redistribution structure portions, acting as an electrically-isolated stiffener to reduce deformation and strain caused by CTE mismatches and material expansion/contraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional redistribution structure without dummy bump region is used, then manufacturing process is simpler, but deformation and strain concentration occur due to CTE mismatch, causing breaks in electrical connections
Solution Approach 1:
The redistribution structure is segmented into functional regions (active redistribution areas) and dummy bump regions. The dummy bump region is further divided into multiple dummy vias arranged in specific patterns. This segmentation allows the structure to be divided into load-bearing electrical connection paths and stress-dissipating dummy elements, reducing strain concentration on actual signal paths while maintaining manufacturing feasibility.
Solution Approach 2:
The dummy bump region acts as an intermediary element between the substrate and the active redistribution structure. It provides a transition zone that absorbs and distributes thermal stress generated by CTE mismatch, preventing direct transmission of deformation forces to the electrical connections. The dummy vias within this region serve as stress mediators that protect the functional redistribution vias from strain-induced breaks.
2Strength
If redistribution structure with enhanced vias and wiring interconnects is used, then resistance to strain and crack generation is improved, but manufacturing precision requirements increase
Solution Approach 1:
The structure implements local quality enhancement by concentrating reinforced vias and wiring interconnects specifically in the dummy bump region and at critical stress points, while maintaining standard design in less critical areas. The dummy vias are strategically positioned to provide localized stress absorption without requiring enhanced precision across the entire redistribution structure. This selective reinforcement approach improves strain resistance where needed while keeping manufacturing precision requirements manageable.
Solution Approach 2:
The dummy bump region with enhanced vias and wiring interconnects serves as a pre-configured cushioning zone that anticipates and absorbs thermal stress before it can propagate to the active electrical connections. The reinforced structure in the dummy region acts as a buffer, preventing crack initiation and propagation in advance. This beforehand cushioning approach strengthens the overall structure against strain while allowing standard manufacturing precision in the active regions.
3Reliability
If dummy bump region is added to reduce deformation, then package reliability is enhanced, but device complexity and manufacturing steps increase
Solution Approach 1:
The dummy bump region is merged with the existing redistribution structure fabrication process rather than being added as a separate post-processing step. The dummy vias are formed using the same via formation processes (drilling, plating, filling) as the active redistribution vias. The wiring interconnects in the dummy region are patterned and deposited alongside the functional wiring layers. This merging approach integrates the reliability-enhancing dummy structure into the standard manufacturing flow, minimizing additional process steps and maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The DBR improves the reliability of chip packages by suppressing deformation and reducing stress on signal-carrying wiring interconnects, enhancing overall package reliability and resistance to strain and crack generation.
Implementation Method 1
a difference in coefficient of thermal expansion (CTE) values between the substrate and various adjoined or proximate components and layers may induce deformation (warpage) within the chip package
Implementation Method 2
acting as an electrically-isolated stiffener to reduce deformation and strain caused by CTE mismatches and material expansion/contraction
Data Source
AI summary
Methods and devices include a chip package structure, including a first semiconductor die, a second semiconductor die, a redistribution structure, and a first underfill material portion located between the redistribution structure and the first semiconductor die and the second semiconductor die. The redistribution structure includes a first redistribution structure portion physically and electrically connected to the first semiconductor die, a second redistribution structure portion physically and electrically connected to the second semiconductor die, and a dummy bump region positioned between and electrically isolated from the first redistribution structure portion and the second redistribution structure portion.