Redistribution Structure for Shorter Inter-Chip Data Paths
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in data signal transmission and power consumption.
Innovation Solution
The semiconductor device incorporates a redistribution structure with a plug structure and redistribution layers, allowing data signals to be transmitted through bonding pads and redistribution layers without passing through conductive features or functional units, thereby reducing transmission distance and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data signals are transmitted through conventional conductive features and functional units, then the transmission path is established, but the transmission distance is long and power consumption is high
Solution Approach 1:
The patent extracts the data signal transmission path from the conventional route through conductive features and functional units, creating a dedicated direct path through bonding pads and redistribution layers. This separation allows data signals to bypass the longer path through logic circuits, thereby reducing transmission distance and power consumption simultaneously.
Solution Approach 2:
The patent introduces bonding pads and redistribution layers as intermediary structures to facilitate direct data signal transmission between chips. These intermediaries provide a specialized transmission path that is optimized for data signals, distinct from the power and control signal paths through functional units.
2Productivity
If semiconductor device dimensions are scaled down, then computing ability is improved, but quality, yield, performance, and reliability deteriorate
Solution Approach 1:
The patent segments the semiconductor device into multiple chips (first chip and second chip) that are bonded together. This segmentation allows each chip to be optimized independently for its specific function while maintaining overall system performance. The redistribution structure further segments the signal paths, allowing data signals to travel through optimized dedicated paths rather than congested scaled-down interconnects.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking with redistribution structures. By adding the vertical dimension with multiple bonding pads and redistribution layers, the device achieves improved computing ability through increased integration density while maintaining reliability through dedicated signal paths that are not constrained by two-dimensional scaling limitations.
3Reliability
If a plug structure is positioned in the inter-dielectric layer, then electrical coupling to functional units is achieved, but the data signal transmission path becomes complex
Solution Approach 1:
The patent applies local quality by positioning the plug structure specifically in the inter-dielectric layer to provide localized electrical coupling to functional units where needed. Meanwhile, the bonding pads and redistribution layers provide a separate localized path for data signals. This spatial differentiation allows each structure to perform its specific function without adding unnecessary complexity to other signal paths.
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.