Redistribution Interconnect Layout for Multi-Die Signal Integrity
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Solution Overview
Problem
Existing semiconductor devices face challenges with signal integrity issues, latency, and IR drop due to high connection density and fine pitch connections, particularly in interconnections between semiconductor dies and tiles, which affect performance and reliability.
Innovation Solution
Implementing a redistribution structure with interconnect structures that extend in various directions, including diagonal paths, to connect semiconductor dies and tiles, reducing impedance and latency, and incorporating silicon bridges for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high connection density and fine pitch connections are used to increase interconnect capacity, then connectivity between semiconductor dies and tiles is improved, but signal integrity deteriorates due to impedance, latency, and IR drop issues
Solution Approach 1:
The patent introduces diagonal interconnect paths in addition to traditional orthogonal (horizontal and vertical) paths, effectively adding a new dimensional approach to routing. This allows signals to traverse shorter distances and avoid congested orthogonal routes, thereby maintaining signal integrity while supporting high connection density and fine pitch requirements
2Adaptability or versatility
If more interconnect structures are added to connect semiconductor dies and tiles, then connectivity is improved, but device complexity increases
Solution Approach 1:
The interconnect structure is segmented into orthogonal paths (horizontal and vertical) and diagonal paths, allowing the system to divide the routing function into distinct segments. This segmentation enables versatile connectivity options while managing complexity by organizing interconnects into modular path types that can be independently routed and controlled
Data Source
AI summary
A semiconductor device includes a plurality of top semiconductor dies. Each of the plurality of top semiconductor dies can be bonded to a bottom semiconductor die. The semiconductor device includes a redistribution structure disposed opposite the plurality of top semiconductor dies from the plurality of bottom semiconductor dies and comprising a plurality of interconnect structures. A top semiconductor die can connect to another top semiconductor die via a first subset of the plurality of interconnect structures.