Redistribution Interconnections for High-Density Semiconductor Stacking
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Solution Overview
Problem
The manufacturing process for semiconductor devices faces challenges in reducing pattern margins and achieving high-speed, high-density chip stacking, particularly in integrating multiple functions into a smaller area, while maintaining efficient fabrication costs.
Innovation Solution
A semiconductor chip design featuring a redistribution interconnection structure formed using a deposition and patterning process, with conductive patterns and insulating layers that allow for efficient electrical connections and packaging, enabling vertical stacking and high-density integration without increasing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are vertically stacked to achieve high-density integration, then the integration density increases, but the manufacturing complexity and precision requirements increase
Solution Approach 1:
The patent transitions from planar 2D interconnection patterns to 3D vertical stacking architecture. Multiple semiconductor chips are stacked vertically with redistribution interconnections established through via holes penetrating insulating layers, enabling high-density integration by utilizing the third dimension (vertical direction) rather than expanding in the horizontal plane.
Solution Approach 2:
The patent divides the interconnection structure into multiple discrete conductive patterns (first, second, third conductive patterns) separated by insulating layers. Each conductive pattern is further segmented into contact portions, line portions, and bonding pad portions, allowing independent formation and precise alignment through sequential deposition and patterning processes.
2Reliability
If multiple conductive patterns are formed using deposition and patterning processes, then the electrical connection efficiency improves, but the fabrication complexity increases
Solution Approach 1:
The patent forms conductive patterns using deposition processes that create thicker conductive layers in regions requiring stronger electrical connections (contact portions) before final patterning. The deposition process is configured to deposit more material in areas where via holes will be formed, ensuring adequate conductive material remains after etching and patterning to maintain low resistance connections.
Solution Approach 2:
The patent varies the thickness parameter of conductive patterns across different regions. Contact portions have greater thickness than line portions, which in turn are thicker than bonding pad portions. This parameter variation optimizes electrical connection efficiency by providing lower resistance paths where needed while reducing material usage and fabrication complexity in other regions.
3Reliability
If contact portions have greater thickness for better electrical connection, then the electrical conductivity improves, but the material consumption increases
Solution Approach 1:
The patent applies different thickness qualities of conductive material to different functional regions. Contact portions (filling via holes) have maximum thickness for optimal electrical connection to pads. Line portions have intermediate thickness for signal transmission. Bonding pad portions have reduced thickness since they interface with external bonding rather than requiring low-resistance through-connectors. This local differentiation improves conductivity where needed while minimizing overall material consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density semiconductor packages with efficient electrical connections and reduced fabrication costs, addressing the challenges of pattern margin reduction and high-speed performance in a compact form factor.
Implementation Method 1
redistribution interconnection structure formed using a deposition and patterning process
Data Source
AI summary
A semiconductor chip is provided including an integrated circuit on a substrate; pads electrically connected to the integrated circuit; a lower insulating structure defining contact holes exposing the pads, respectively; and first, second and third conductive patterns electrically connected to the pads. The second conductive pattern is between the first conductive pattern and the third conductive pattern when viewed from a plan view. Each of the first to third conductive patterns includes a contact portion filling the contact hole, a first conductive line portion extending in one direction on the lower insulating structure, and a bonding pad portion. Ends of the bonding pad portions of the first and third conductive patterns protrude in the one direction as compared with an end of the bonding pad portion of the second conductive pattern when viewed from a plan view.