3D Package Redistribution Interconnects Parallel Fabrication
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in achieving shorter cycle times and higher yields, particularly in forming 3D packages with top and bottom side redistribution layers, which are prone to defects and contamination, leading to increased costs and inventory waste.
Innovation Solution
The method involves simultaneous fabrication of top and bottom side redistribution interconnect structures on separate manufacturing lines, with thorough testing to ensure only known good units are combined, reducing cycle time and improving yield by avoiding defective units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If top and bottom side redistribution interconnect structures are formed sequentially on the same manufacturing line, then manufacturing precision can be maintained, but cycle time increases and productivity decreases
Solution Approach 1:
The manufacturing process is divided into two separate manufacturing lines: a first manufacturing line for forming the bottom side redistribution interconnect structure and a second manufacturing line for forming the top side redistribution interconnect structure. This segmentation allows parallel processing of different structural layers, reducing overall cycle time while maintaining quality control on each dedicated line.
Solution Approach 2:
The process transitions from sequential single-line manufacturing to parallel multi-line manufacturing, adding a temporal dimension to the production process. By operating multiple manufacturing lines simultaneously, the patent achieves faster throughput without compromising the precision of individual structure formations.
2Productivity
If units are combined before thorough testing, then productivity increases, but yield decreases due to defects and contamination
Solution Approach 1:
The patent implements comprehensive testing of the bottom side redistribution interconnect structure before combining it with the top side structure. This preliminary testing identifies and isolates defective units early in the process, preventing contamination and defects from propagating to the final assembled product, thereby maintaining high yield.
Solution Approach 2:
A testing and selection process acts as an intermediary between structure formation and final assembly. This intermediary step filters out defective units through electrical testing and visual inspection, ensuring that only known good units proceed to the combining stage, thus protecting the final product quality.
3Manufacturing precision
If laser drilling is used to form vertical interconnect structures, then manufacturing precision is improved, but cycle time increases and equipment cost increases
Solution Approach 1:
The patent extracts and eliminates the laser drilling step from the manufacturing process. Instead of using laser drilling to form vertical interconnect structures, the invention employs alternative interconnection methods such as conductive pillars formed through electroplating or electroless plating, which reduce cycle time and equipment costs while maintaining adequate precision.
Solution Approach 2:
The patent replaces expensive, time-consuming laser drilling with more economical forming methods. By using electroplating or electroless plating to create conductive pathways, the process achieves the necessary precision at lower equipment cost and faster processing speed, effectively substituting a high-cost method with a more efficient alternative.
Data Source
AI summary
A method of making a semiconductor device comprises the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while simultaneously forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU, and disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD. A resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.