Redistribution Layer Capacitors for Noise-Immune Semiconductor Layouts

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Solution Overview

Problem

In advanced semiconductor processes, the limited layout area restricts the space for decoupling capacitors, necessitating an increase in their number to enhance noise immunity in high-speed integrated circuits affected by electrical noise.

Innovation Solution

A semiconductor device incorporating powering and grounding redistribution layers that form capacitors, allowing for additional decoupling capacitance without requiring additional masks or metal layers, by alternately arranging these layers and connecting them with bridges to enhance routing mobility and electrical testing convenience.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of decoupling capacitors is increased to enhance noise immunity, then noise immunity is improved, but layout area is exceeded

Engineering Contradiction:
Improvenoise immunityVSAvoidlayout area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the decoupling capacitor function with the power distribution network by integrating capacitive structures directly into the power and ground redistribution layers. This combination allows the PDN to provide both power delivery and decoupling functions simultaneously, improving noise immunity without requiring separate capacitor components that would consume additional layout area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The power and ground redistribution layers serve multiple functions: they distribute power throughout the device, provide grounding paths, and simultaneously act as decoupling capacitors. This multi-functionality eliminates the need for dedicated capacitor areas, as the same structural elements perform both power distribution and noise filtering roles.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If additional decoupling capacitors are added to reduce inductive noise, then noise immunity is improved, but device complexity increases

Engineering Contradiction:
Improvenoise immunityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the decoupling capacitor functionality with the existing power distribution network structures. By integrating capacitive elements into the power and ground redistribution layers, the design eliminates the need for separate capacitor components and their associated interconnections, thereby reducing device complexity while maintaining noise immunity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The redistribution layers perform multiple functions including power delivery, grounding, and noise filtering. This multi-functionality reduces the overall number of components needed in the device, simplifying the design while achieving improved noise immunity through the integrated capacitive structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively increases decoupling capacitance, improving noise immunity and routing mobility while maintaining compact design feasibility across generations.

Implementation Method 1

each of the powering redistribution layers and a corresponding one of the grounding redistributions layers form a capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS20230361019A1Semiconductor device
Publication Date: 2023.11.09 NAN YA TECH
  • US20230361019A1 patent drawing
  • US20230361019A1 patent drawing
  • US20230361019A1 patent drawing

AI summary

The present disclosure provides a semiconductor device. The semiconductor device includes a wafer, powering redistribution layers, and grounding redistribution layers. The powering redistribution layers are disposed on the wafer. The grounding redistribution layers are disposed on the wafer, in which each of the powering redistribution layers and a corresponding one of the grounding redistributions layers form a capacitor.