Redistribution-Layer Semiconductor Package for Wire-Free Chip Interconnects
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Solution Overview
Problem
Existing semiconductor apparatuses for power electronic devices face challenges in heat dissipation and wire deformation during transfer molding, and the reduction in size of semiconductor chips makes it difficult to use bonding wires for connections, leading to increased wiring inductance and noise generation.
Innovation Solution
The semiconductor apparatus employs redistribution layers to electrically connect semiconductor chips and external connection terminals without bonding wires, using a layered structure with insulating and conductor layers to reduce wiring length and prevent wire deformation, while also allowing for high-speed switching operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wire is used to connect semiconductor chips and external terminals, then electrical connection is achieved, but wire deformation occurs during transfer molding and wiring inductance increases
Solution Approach 1:
The patent extracts and eliminates the bonding wire from the system by using redistribution layers formed directly on the semiconductor chip and substrate. This removes the source of wire deformation and excessive inductance while maintaining electrical connection functionality through integrated copper traces instead of separate wire bonds
Solution Approach 2:
The patent merges the electrical connection function with the substrate and chip structure by integrating redistribution layers directly into the packaging substrate and chip architecture. The conductor layers are combined with insulating layers to form a unified multi-layer structure that provides both mechanical support and electrical connectivity without requiring separate bonding wires
2Volume of moving object
If semiconductor chip size is reduced, then device miniaturization is achieved, but bonding wire connection becomes difficult and wiring inductance increases
Solution Approach 1:
The patent transitions from two-dimensional wire bonding to three-dimensional integrated circuit architecture by stacking multiple conductor and insulator layers vertically. This allows electrical connections to be made in the vertical dimension through redistribution layers, enabling compact chip designs without the limitations of planar wire bonding
3Object-affected harmful factors
If redistribution layer is used to connect semiconductor chips without bonding wire, then wire deformation is prevented and wiring inductance is reduced, but device complexity increases
Solution Approach 1:
The redistribution layers serve multiple functions simultaneously: they provide electrical connection, thermal management pathways, and mechanical support structure. The same conductor layers that reduce inductance also function as heat sinks and structural elements, eliminating the need for separate components and reducing overall device complexity despite the integrated design
Data Source
AI summary
A semiconductor apparatus includes (i) semiconductor chips including a power semiconductor chip including a switch and a control semiconductor chip including a control circuit configured to control the switch, (ii) redistribution layers including a first redistribution layer that electrically connects a first semiconductor chip to a second semiconductor chip from among the semiconductor chips, (iii) a first sealing material that seals the semiconductor chips and the redistribution layers, (iv) an insulating substrate including a first conductor layer, a second conductor layer and an insulating layer between the first and second conductor layers, in which the insulating substrate is fixed to the first sealing material to be opposed to the semiconductor chips and the redistribution layers, and (v) a second sealing material that seals the insulating substrate and the first sealing material.