Redistribution Layer Packaging for Dense Multi-Chip Interconnects

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The challenge in integrating multiple active chips in a package device is the high requirement for interconnection efficiency and the complexity and cost of manufacturing, particularly as chips with more functions or higher computing power necessitate improved interconnection structures.

Innovation Solution

A package device structure is designed with a redistribution layer, conductive pillars, and encapsulants, featuring a first and second redistribution layer with conductive pillars and encapsulants to facilitate efficient chip coupling and reduce manufacturing complexity and cost, utilizing a method that forms these layers sequentially on a carrier and removes it post-manufacturing to avoid warping and improve alignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple active chips are integrated in the same package device to meet customer requirements, then the functionality and computing power are improved, but the interconnection efficiency requirement and manufacturing complexity increase

Engineering Contradiction:

ImprovefunctionalityVSAvoidmanufacturing complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The package device is divided into multiple independent chip modules (first chips, second chips) that can be separately manufactured and then integrated. Each chip has its own encapsulant and connection structures, allowing parallel processing and reducing overall manufacturing complexity while maintaining high functionality

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar chip arrangement to three-dimensional stacked configuration with chips positioned at different heights (first chips on first redistribution layer, second chips on second redistribution layer). This vertical integration increases functionality without proportionally increasing manufacturing complexity by utilizing the third dimension

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Power

If higher computing power chips are used, then performance is improved, but the interconnection structure requirements become more stringent

Engineering Contradiction:

Improvecomputing powerVSAvoidinterconnection structure precision

Core Design Contradiction:

PowerVSManufacturing precision

Solution Approach 1:

Redistribution layers (first redistribution layer, second redistribution layer) are introduced as intermediary structures between chips and external connections. These layers provide signal routing and impedance matching, enabling high-performance chips to be interconnected with standard external interfaces while maintaining signal integrity and reducing manufacturing precision requirements on direct chip-to-chip connections

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces direct mechanical/electrical contact between chips with electromagnetic field-based interconnection through redistribution layers and conductive pillars. This substitution allows for greater design flexibility and reduces the stringent mechanical alignment precision requirements that would otherwise be needed for direct chip-to-chip bonding

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Speed

If interconnection efficiency between chips is improved through complex structures, then signal transmission is enhanced, but manufacturing cost and complexity increase

Engineering Contradiction:

Improvesignal transmission efficiencyVSAvoidmanufacturing cost

Core Design Contradiction:

SpeedVSEase of manufacture

Solution Approach 1:

The redistribution layers serve multiple functions simultaneously: they provide signal routing, impedance transformation, mechanical support, and thermal management pathways. This multi-functionality achieves high signal transmission efficiency without requiring separate specialized structures for each function, thereby controlling manufacturing cost

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines multiple interconnection functions into integrated structures where conductive pillars, redistribution layers, and encapsulants work together as a unified system. The underfill material simultaneously provides mechanical reinforcement, stress relief, and electrical insulation. This merging reduces the number of discrete manufacturing steps and lowers overall production cost while maintaining high signal transmission efficiency

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20260018567A1Package device and manufacturing method thereof

Publication Date: 2026.01.15 POWERTECH TECHNOLOGY INC

AI summary

A package device and a manufacturing method thereof are provided. The package device includes a package structure, a redistribution layer, an underfill layer, a plurality of conductive pillars, another redistribution layer, and an encapsulant. The underfill layer is disposed between the package structure and the redistribution layer, and the conductive pillars and the package structure are disposed side by side between the redistribution layers. The encapsulant is disposed between the redistribution layers and surrounds the package structure and the conductive pillars.