Redistribution Layer Structure for Flat Fine-Pitch Via Topology
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Solution Overview
Problem
The existing redistribution layer (RDL) process in semiconductor devices faces challenges with via hole size, leading to topology issues such as bending and sagging, which result in electrical short circuits and reduced reliability, especially as chip sizes decrease and patterns become finer.
Innovation Solution
The proposed redistribution layer structure includes a first insulating layer with strategically placed openings and unetched portions to improve flatness, accompanied by a wiring member layer that fills these openings, thereby maintaining electrical connectivity while preventing bending and sagging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the via hole is large to improve electrical connectivity, then electrical connectivity is improved, but topology problems such as bending and sagging occur in the redistribution layer
Solution Approach 1:
The patent divides the insulating layer into multiple segments: a first insulating layer with via holes and a second insulating layer with unetched portions. This segmentation allows the via holes to be smaller for better topology while the unetched portions provide structural support to prevent bending and sagging, thus resolving the contradiction between via hole size and redistribution layer flatness.
Solution Approach 2:
The patent applies different structural qualities to different regions: the first insulating layer has via holes for electrical connectivity, while the second insulating layer has unetched portions specifically positioned to provide local mechanical support. This local differentiation allows small via holes without compromising overall structural integrity, solving the topology flatness problem while maintaining electrical connectivity.
2Area of moving object
If the size of the chip is reduced and patterns become finer, then chip size is reduced, but via hole size must be reduced which exacerbates topology problems
Solution Approach 1:
By segmenting the insulating structure into two layers with different functions, the patent enables the via holes to be scaled down with chip size while the unetched portions in the second insulating layer compensate for the reduced structural support, preventing topology problems even as chip dimensions decrease.
Solution Approach 2:
The patent introduces a vertical dimension by creating a two-layer insulating structure, where the second insulating layer with unetched portions provides additional structural dimension to compensate for the reduced horizontal via hole size, allowing fine-pitch scaling without topology degradation.
3Reliability
If the via hole size is large to ensure electrical connectivity, then electrical connectivity improves, but bending and sagging occur causing electrical short circuits
Solution Approach 1:
The patent segments the electrical connection path through multiple via holes in the first insulating layer, each via hole being small enough to prevent sagging, while the unetched portions in the second insulating layer provide mechanical reinforcement to prevent the redistribution layer from bending and causing short circuits, thus maintaining electrical connectivity without harmful effects.
Solution Approach 2:
The unetched portions in the second insulating layer act as pre-positioned structural cushions that prevent bending and sagging before they can cause electrical short circuits. This proactive structural support eliminates the harmful effects associated with large via holes while maintaining necessary electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the topology and flatness of the redistribution layer, reducing device defects and improving reliability by securing excellent electrical connectivity without the drawbacks of large via holes.
Implementation Method 1
forming a seed layer, forming a mask pattern, electroplating a wiring layer
Data Source
Figure 1A~1B
Figure 2A~3A
Figure 3B~4
AI summary
Disclosed are a redistribution layer structure, a method of forming a redistribution layer structure, a semiconductor package device including a redistribution layer structure, and a method of manufacturing a semiconductor package device including a redistribution layer structure. The semiconductor package device may include a redistribution layer structure, wherein the redistribution layer structure may include a first insulating layer having one or more openings open to a target region and an unetched portion configured to improve the flatness of the redistribution layer structure in the remaining region excluding the one or more openings in the space corresponding to the target region and a first wiring member layer disposed on the first insulating layer so as to at least partially fill the one or more openings.