Redistribution Layer Guard Layout for Via Spacing and Isolation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing chip-to-chip communication in semiconductor packages is not satisfactory in all aspects, particularly in terms of conductive feature complexity and efficiency, especially for I/O signals.

Innovation Solution

A redistribution layer with guard members is introduced, featuring a dielectric stack and conductive connections, where guard members are arranged around power/ground connections to reduce spacing and shield signal connections, enhancing electrical isolation and reducing noise coupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If guard members are added around power/ground connections to shield signal connections, then electrical isolation and noise coupling reduction are improved, but device complexity and manufacturing complexity increase

Engineering Contradiction:
Improveelectrical isolationVSAvoidconductive feature complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The guard members are nested within the existing redistribution layer structure, positioned between the signal connections and power/ground connections. This nesting approach allows the guard members to be integrated into the existing conductive feature hierarchy without requiring separate isolation layers or additional structural elements, thereby improving electrical isolation while minimizing increases in device complexity

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The guard members act as intermediary conductive elements positioned between signal connections and power/ground connections. These intermediary structures provide electrostatic shielding and electrical isolation by creating intermediate potential zones, reducing noise coupling while maintaining a relatively simple manufacturing process that builds upon existing redistribution layer fabrication techniques

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of stationary object

If spacing between conductive vias is reduced to improve chip area utilization, then device area usage is improved, but electrical isolation and noise coupling performance deteriorate

Engineering Contradiction:
Improvechip areaVSAvoidnoise coupling
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The guard members are nested within the available space between conductive vias, utilizing the vertical and lateral dimensions of the redistribution layer structure. This nesting allows effective noise shielding to be achieved within the constrained horizontal spacing, enabling reduced via spacing while maintaining electrical isolation through the vertically-integrated guard member structures

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The solution moves the isolation function from the horizontal plane to the vertical dimension by implementing guard members as vertically-extending conductive structures. This dimensional transition allows noise shielding and electrical isolation to be achieved in the vertical space between signal and power/ground connections, enabling tighter horizontal spacing between conductive vias while maintaining noise coupling performance

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution allows for reduced spacing between conductive vias while maintaining effective electrical isolation, thereby improving communication efficiency and reducing device area usage.

Implementation Method 1

guard members are arranged around power/ground connections to reduce spacing and shield signal connections, enhancing electrical isolation and reducing noise coupling

Methodology Applied
Scientific EffectElectrostatic shielding: Faraday Cage

Data Source

PatentUS20250253225A1Redistribution layer having guard members and method of manufacturing the same
Publication Date: 2025.08.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250253225A1 patent drawing
  • US20250253225A1 patent drawing
  • US20250253225A1 patent drawing

AI summary

A redistribution layer, a semiconductor device, and a method of manufacturing the semiconductor device are provided. The redistribution layer includes a dielectric stack, a plurality of signal connections, a plurality of power/ground connections, and a plurality of guard members. The dielectric stack is disposed on the substrate. The plurality of signal connections penetrate through the dielectric stack. The plurality of power/ground connections extend through the dielectric stack. The plurality of guard members are disposed in the dielectric stake and arranged respectively around the plurality power/ground connections.