Redistribution-Layer Semiconductor Package for Dense Reliable Integration
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving a balance between size reduction, increased integration density, and improved electrical and reliability characteristics.
Innovation Solution
The semiconductor package incorporates a first and second redistribution layer, passive devices, a bridge structure, and conductive structures, with a specific configuration that includes a first semiconductor chip and chip stacks, to enhance electrical connectivity and reduce package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor package structure with PCB and mounted chips is used, then ease of manufacture is maintained, but device size is large and integration density is low
Solution Approach 1:
The patent transitions from a planar PCB mounting structure to a three-dimensional stacked architecture where semiconductor chips, passive devices, and redistribution layers are vertically integrated. This vertical stacking enables significant reduction in package footprint while maintaining high integration density and electrical connectivity through multiple redistribution layers positioned at different heights.
Solution Approach 2:
The patent implements nested structures where passive devices are embedded within or alongside conductive structures and redistribution layers. The conductive structures are positioned between redistribution layers, creating a nested arrangement that maximizes space utilization and achieves high integration density without increasing package volume.
2Quantity of substance
If integration density is increased through more components, then functionality is improved, but electrical characteristics and reliability deteriorate due to congestion
Solution Approach 1:
The patent divides the package into multiple functional layers including first and second redistribution layers, conductive structures, passive devices, and semiconductor chips positioned at different vertical levels. This segmentation distributes electrical connections and signal paths across multiple layers, preventing congestion and maintaining signal integrity while achieving high integration density.
Solution Approach 2:
The conductive structures serve as intermediary elements positioned between the first and second redistribution layers. These conductive structures provide electrical connection pathways that mediate between different functional blocks, enabling dense integration while maintaining reliable electrical connectivity through dedicated connection routes that prevent signal interference.
3Volume of moving object
If package size is reduced, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent forms conductive structures and passive devices on the first redistribution layer before bonding the second redistribution layer. This preliminary formation of interconnection structures simplifies the overall manufacturing process by establishing electrical pathways in advance, reducing the complexity of subsequent assembly steps while enabling compact package design.
Solution Approach 2:
The patent combines multiple fabrication operations into integrated process steps. The conductive structures and passive devices are formed using the same semiconductor manufacturing processes on the first redistribution layer, and the second redistribution layer is bonded in a single step, merging what would otherwise be separate complex operations into a streamlined manufacturing sequence.
Data Source
AI summary
A semiconductor package may include a first redistribution layer, a passive device disposed on a top surface of the first redistribution layer, a bridge structure disposed on the top surface of the first redistribution layer and laterally spaced apart from the passive device, a second redistribution layer disposed on and electrically connected to the passive device and the bridge structure, conductive structures disposed between the first redistribution layer and the second redistribution layer and laterally spaced apart from the passive device and the bridge structure, a first semiconductor chip mounted on a top surface of the second redistribution layer, and a second semiconductor chip mounted on the top surface of the second redistribution layer. The conductive structures may include a signal structure and a ground/power structure, which is laterally spaced apart from the signal structure and has a width larger than the signal structure.