Redistribution Layer Parallel Traces for Faster Chip Interconnects
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Solution Overview
Problem
Conventional redistribution layers in microelectronic devices exhibit high electrical resistance and capacitance, which can affect signal transmission speed and device performance, especially as semiconductor dies become more complex and miniaturized.
Innovation Solution
The use of multiple parallel traces in redistribution layers, stacked or arranged side-by-side, coupled by conductive vias and coupling traces, to reduce electrical resistance and capacitance, allowing for lower insertion loss and higher signal transmission speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional single-trace redistribution layers are used, then device structure is simple, but electrical resistance is high and signal transmission speed is reduced
Solution Approach 1:
The patent divides a single trace into multiple parallel traces within the redistribution layer. Each trace carries a portion of the signal current, effectively reducing the overall electrical resistance and capacitance. This segmentation allows the RDL to achieve high-speed signal transmission while maintaining a manageable structural complexity through systematic multi-layer design.
Solution Approach 2:
The patent transitions from a two-dimensional single-trace layout to a three-dimensional multi-layer structure with traces stacked vertically and connected via vias. This dimensional change enables multiple parallel conduction paths without significantly increasing the lateral footprint, thereby reducing resistance and capacitance while controlling overall device complexity.
2Area of moving object
If trace dimensions are reduced for miniaturization, then device footprint is smaller, but electrical resistance increases
Solution Approach 1:
The patent segments the current path into multiple parallel traces, each with reduced individual dimensions for miniaturization. The combined effect of multiple parallel traces maintains low overall resistance while achieving a smaller total footprint, as the traces are distributed across multiple layers rather than requiring a single large lateral area.
Solution Approach 2:
The patent utilizes the vertical dimension through multi-layer stacking to accommodate multiple parallel traces. This allows each trace to have smaller lateral dimensions for miniaturization while the vertical stacking provides additional conduction paths, maintaining low resistance despite reduced individual trace dimensions.
3Reliability
If multiple parallel traces are used, then electrical resistance and capacitance are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the RDL into multiple standardized layers with traces and vias, each formed through established semiconductor fabrication processes. This modular segmentation allows complex multi-trace structures to be manufactured using conventional step-by-step deposition, etching, and patterning techniques, making the manufacturing process manageable despite the increased number of components.
Solution Approach 2:
The patent employs standard multi-layer PCB/RDL fabrication techniques where traces are formed on different planes and connected through vias. This approach leverages existing manufacturing capabilities for multi-layer structures, making the production of complex parallel trace configurations feasible through proven industrial processes rather than requiring novel manufacturing methods.
Data Source
AI summary
An interposer includes an upper surface for coupling to a chip, a lower surface for coupling to a package substrate, and redistribution layers between the upper surface and the lower surface and including routed conductive lines. A respective one of the routed conductive lines extend between a first location and a second location and includes two or more traces extending substantially in parallel between the first location and the second location. Related devices and methods are also described.