Redistribution Layer Plating Uniformity via Planarization

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Solution Overview

Problem

Modern electronic packages face challenges in achieving reliable interconnections between chip-to-package and chip-to-substrate due to the need for advanced processes and materials that can handle complex geometries and ensure consistent connectivity.

Innovation Solution

A manufacturing method involving a carrier with dielectric layers, seed layers, and metallic patterns is used to form connection structures with protruded portions and conductive balls, allowing for improved plating uniformity and reliability of redistribution layers, even on uneven surfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional manufacturing processes are used for connection structures, then the process is simpler, but the plating uniformity and reliability of redistribution layers deteriorate on uneven surfaces

Engineering Contradiction:
Improveplating uniformityVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

A planarization layer is formed over the connection structures before subsequent processing steps. This preliminary action creates a flat surface that enables uniform plating in later stages, resolving the plating uniformity issue without requiring complex in-situ planarization equipment

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The planarization layer acts as an intermediary between the uneven connection structures and the subsequent metallic layers. This intermediate layer absorbs the surface irregularities and provides a uniform substrate for plating, eliminating the need for complex direct plating processes on uneven surfaces

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If advanced processes and materials are used to ensure reliable interconnections, then the connection reliability improves, but the device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveinterconnection reliabilityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The manufacturing process is segmented into distinct stages: forming connection structures, forming a planarization layer, and then subsequent plating steps. This segmentation allows each stage to be optimized independently, ensuring reliable interconnections through controlled processes rather than attempting complex single-step operations

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The introduction of the planarization layer changes the surface topology parameter from uneven to flat. This parameter change enables standard plating processes to achieve uniform thickness and reliable connections, avoiding the need for complex adaptive plating equipment or materials

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the reliability of interconnections by providing a flatter surface for subsequent layers and improving the uniformity of metallic patterns, thereby increasing the reliability of chip-to-package and chip-to-substrate connections.

Implementation Method 1

A metallic pattern is formed on the first seed layer

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS11251142B2Method of fabricating package structure
Publication Date: 2022.02.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11251142B2 patent drawing
  • US11251142B2 patent drawing
  • US11251142B2 patent drawing

AI summary

A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.