Redistribution Layer Protrusions for Chip Package Reliability
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Solution Overview
Problem
Existing chip packaging technologies face challenges in redistributing increasing numbers of chip contacts on a downsized chip surface, leading to electrical reliability issues and contamination due to overflow of encapsulation material, and insufficient bonding strength after carrier removal.
Innovation Solution
A package structure and manufacturing method involving a redistribution layer formed on an under bump supporting layer with openings, where the chip is disposed on the redistribution layer, encapsulated, and solder balls are placed in the openings to ensure structural support and alignment, enhancing bonding strength and preventing material overflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the redistribution layer is formed completely flat and smooth on the carrier, then the manufacturing process is simplified, but the bonding strength for connecting the chip becomes insufficient
Solution Approach 1:
The patent introduces protrusions (raised structures) on the carrier surface, transforming the completely flat surface into a curved/non-uniform surface. These protrusions provide mechanical interlocking features that enhance bonding strength while maintaining manufacturing simplicity through standard photolithography and etching processes.
Solution Approach 2:
The protrusions are formed on the carrier before the redistribution layer is deposited. This preliminary structuring of the carrier surface ensures that when the redistribution layer is formed and subsequent bonding occurs, the enhanced mechanical interlocking is already in place, preparing the structure for stronger bonding without complicating the main manufacturing flow.
2Area of stationary object
If encapsulation material is used to package the chip first, then the chip area is increased, but the encapsulation material may overflow and contaminate the active surface of the chip
Solution Approach 1:
The patent segments the carrier surface into distinct functional zones: an active area for chip mounting and peripheral areas for encapsulation material containment. The protrusions are strategically positioned to create physical barriers that segment the flow path of encapsulation material, preventing it from reaching the chip active surface while still allowing the encapsulation to provide its area-increasing function.
Solution Approach 2:
The protrusions act as intermediary structures between the encapsulation material and the chip active surface. They serve as physical barriers that intercept and redirect the encapsulation material flow, preventing direct contact with the chip while maintaining the encapsulation's beneficial effects.
3Quantity of substance
If the number of chip contacts increases, then the connectivity is improved, but the downsizing of chip area makes it difficult to redistribute contacts on the chip surface
Solution Approach 1:
The patent moves the contact redistribution function from the two-dimensional chip surface to the three-dimensional carrier structure. By forming protrusions with varying heights and positions on the carrier, the system creates additional spatial dimensions for contact arrangement, allowing high-density contact patterns to be achieved without increasing the chip footprint area.
Data Source
AI summary
A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.